Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
2.4 Subrate Switching for the Ambassador Family (continued)
2.4.4 Using the Existing Architecture (continued)
Figure 13 illustrates the changes to the architecture of the Ambassador family.
The subrate enable bit (GMODE bit 5) is intended as a static control; that is, if subrate is going to be performed,
this bit must be set before attempting any CAM operations. The internal circuit monitors the state of this bit, and
performs different command protocols depending on its value. For a T8100A device with subrate disabled, the pro-
tocol is identical to that of a T8100; that is, the SCT register is not used, writes to it and reads from it are disabled,
and the internal state machine expects (and will only handle) three IDR reads for an RDC command. For a T8100A
device with subrate enabled, writes to and reads from SCT are enabled, and the internal state machine expects
(and will only handle) four IDR reads for an RDC command.
SUBRATE
ENABLE
CAMS
TAGS
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WRITE ENABLES
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WORD
ADDRESS
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DATA
BUFFER 0
DATA
BUFFER 1
5-7151F
Figure 13. Modifications for Subrate Switching
Lucent Technologies Inc.
41
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