Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands (continued)
H26
H27
L13
H0
H1
L0
H2
H3
L1
H4
H5
L2
H6
H7
L3
H8
H9
L4
H10
H11
L5
H12
H13
L6
H14
H15
L7
H16
H17
L8
H18
H19
L9
H20
H21
L10
H22
H23
L11
H24
H25
L12
H28
H29
L14
H30
H31
L15
976 ns
61 ns
MICRO-
PRO-
CESSOR
MICRO-
PRO-
CAM-E
CAM-O
CAM-L
H12 WRITE
H12 READ
H13 READ
L6 READ
CESSOR
MICRO-
PRO-
CESSOR
MICRO-
PRO-
CESSOR
H13
WRITE
MICRO-
PRO-
MICRO-
PRO-
L6 WRITE
CESSOR
CESSOR
MICRO-
PRO-
CESSOR
MICRO-
H12 WRITE
H12 READ
H13 READ
C0-SRAM
C1-SRAM
CL-SRAM
PRO-
CESSOR
MICRO-
PRO-
CESSOR
MICRO-
PRO-
CESSOR
H13
WRITE
MICRO-
PRO-
CESSOR
MICRO-
PRO-
CESSOR
L6 WRITE
L6 READ
ODD (H13)
EVEN (H12)
MICRO-
EVEN (H12)
LOCAL (L6)
ODD (H13)
DATA SRAM WRITES
PRO-
CESSOR
MICRO-
PRO-
CESSOR
DATA SRAM READS
LOCAL (L6)
CLOCK
15.25 ns
5-6109F
Figure 10. Simplified H-Bus State Timing, 65.536 MHz Clock
Lucent Technologies Inc.
33