Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.4 LBS: Local Stream Control, 0x0C
The normal mode of operation for local streams is serial in/serial out, but parallel modes are available. Modes and
data rates are controlled by register LBS. The mapping is shown below. See the preceding pages for a full descrip-
tion.
Table 42. LBS: Local Stream Control, 0x0C
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LBS
—
P/S
SGa
SGb
SGc
Symbol
Bit
Description
P/S
7—6
P/S = 00. Serial In/Serial Out.
The SGa bits control the group A pins, SGb bits control the group B pins, and SGc bits
control the group C pins. As serial streams, input and output rates within the same
group are constrained to be identical so both inputs and outputs share the same 2 bits
for programming.
The SGb bits are enabled when SGa ≠ 11.
The SGc bits are enabled when SGb ≠ 11.
P/S = 01. Serial In/Parallel Out.
SGa sets input (serial) rate using the rate definition within this table.
SGb is reserved.
SGc sets the output (parallel) rate using the rate definition within this table.
P/S = 10. Parallel In/Serial Out.
SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (serial) rate.
P/S = 11. Parallel In/Parallel Out.
SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (parallel) rate.
SGa
SGb
SGc
5—4
3—2
1—0
SGa = 00, 3-state.
SGa = 01, 2.048 Mbits/s.
SGa = 10, 4.096 Mbits/s.
SGa = 11, 8.192 Mbits/s.
SGb = 00, 3-state.
SGb = 01, 2.048 Mbits/s.
SGb = 10, 4.096 Mbits/s.
SGb = 11, 8.192 Mbits/s.
SGc = 00, 3-state.
SGc = 01, 2.048 Mbits/s.
SGc = 10, 4.096 Mbits/s.
SGc = 11, 8.192 Mbits/s.
There are no additional registers required for addressing the local memory other than the main address registers
(discussed in Section 2.1 Register/Memory Maps). The data and connection memory locations (T8100A, T8105
only) can be queried for their contents by indirect reads through the main address registers; however, the memory
locations are referred to by the stream and time-slot designators, rather than physical address locations, to simplify
the queries.
28
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