Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 48.
(continued)
Programmable I/O (PIO) Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
Output Delays (TJ = 85 °C, VDD = min, CL = 50 pF)
Output to Pad (OUT2, OUT1 direct to pad):
Fast
Slewlim
Sinklim
OUTF_DEL
OUTSL_DEL
OUTSI_DEL
—
—
—
5.09
7.86
9.41
—
—
—
4.21
6.49
7.98
—
—
—
2.63
3.49
8.08
—
—
—
2.17 ns
2.91 ns
7.32 ns
3-state Enable/Disable Delay (TS to pad):
Fast
Slewlim
Sinklim
TSF_DEL
TSSL_DEL
TSSI_DEL
—
—
—
4.93
7.70
9.25
—
—
—
4.09
6.37
7.86
—
—
—
2.33
3.00
7.95
—
—
—
1.88 ns
2.41 ns
7.23 ns
Local Set/Reset (async) to Pad (LSR to pad):
Fast
Slewlim
Sinklim
OUTLSRF_DEL
OUTLSRSL_DEL
OUTLSRSI_DEL
—
—
—
9.03
11.79
13.35
—
—
—
7.25
9.53
11.02
—
—
—
4.96
5.82
10.38
—
—
—
3.94 ns
4.67 ns
9.10 ns
Global Set/Reset to Pad (GSRN to pad):
Fast
Slewlim
Sinklim
OUTGSRF_DEL
OUTGSRSL_DEL
OUTGSRSI_DEL
—
—
—
8.30
11.06
12.62
—
—
—
6.69
8.97
10.46
—
—
—
4.39
5.07
10.02
—
—
—
3.46 ns
3.99 ns
8.81 ns
Output FF Setup Timing:
Out to ExpressCLK (OUT[2:1] to ECLK)
Out to Clock (OUT[2:1] to CLK)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
OUTE_SET
OUT_SET
OUTCE_SET
OUTLSR_SET
0.00
0.00
0.91
0.41
—
—
—
—
0.00
0.00
0.67
0.32
—
—
—
—
0.00
0.00
0.56
0.26
—
—
—
—
0.00
0.00
0.45
0.24
—
—
—
—
ns
ns
ns
ns
Output FF Hold Timing:
OUTE_HLD
OUT_HLD
OUTCE_HLD
OUTLSR_HLD
Out from ExpressCLK (OUT[2:1] from ECLK)
Out from Clock (OUT[2:1] from CLK)
Clock Enable from Clock (CE from CLK)
Local Set/Reset (sync) from Clock (LSR from
CLK)
0.73
0.73
0.00
0.00
—
—
—
—
0.58
0.58
0.00
0.00
—
—
—
—
0.36
0.36
0.00
0.00
—
—
—
—
0.29
0.29
0.00
0.00
—
—
—
—
ns
ns
ns
ns
Clock to Pad Delay (ECLK, SCLK to pad):
Fast
Slewlim
Sinklim
OUTREGF_DEL
OUTREGSL_DEL
OUTREGSI_DEL
—
—
—
6.71
9.47
11.03
—
—
—
5.44
7.71
9.20
—
—
—
3.56
4.42
8.98
—
—
—
2.78 ns
3.52 ns
7.94 ns
OD_DEL
Additional Delay If Using Open Drain
—
0.20
—
0.16
—
0.10
—
0.08 ns
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.
Lucent Technologies Inc.
113
AGERE [ AGERE SYSTEMS ]
