Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Special Function Blocks Timing
Table 49. Microprocessor Interface (MPI) Timing Characteristics
DD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Cxx Commercial: V
OR3Txxx Commercial: V
<
<
<
<
A
T +85 °C.
DD
A
T
DD
= 3.0 V to 3.6 V, 0 °C
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Speed
Parameter
Symbol
–4
–5
–6
–7
Unit
Min Max Min Max Min Max Min Max
Interface Timing (TJ = 85 °C, VDD = min)
PowerPC
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
Burst Inhibit Delay to High Impedance
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MPI_ACK low)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
TA_DEL
BI_DEL
TA_DELZ
BI_DELZ
WD_SET
WD_HLD
A_SET
A_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
—
—
—
11.6
11.6
(2)
—
—
—
9.3
9.3
(2)
—
—
—
8.0
8.0
(2)
—
—
—
6.8 ns
6.8 ns
(2)
ns
ns
(2)
(2)
(2)
(2)
—
—
—
—
0.0
0.0
0.0
0.0
0.0
0.0
0.3
0.0
—
—
—
—
—
—
—
—
—
3.3
7.0
0.0
0.0
0.0
0.0
0.0
0.0
.25
0.0
—
—
—
—
—
—
—
—
—
2.6
5.4
0.0
0.0
0.0
0.0
0.0
0.0
.14
0.0
—
—
—
—
—
—
—
—
—
2.3
4.2
0.0
0.0
0.0
0.0
0.0
0.0
.12
0.0
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
1.9 ns
3.6 ns
User Read/Write Delay (pad to URDWR_DEL)
URDWR_DEL
—
—
—
—
Interface Timing (TJ = 85 °C, VDD = min)
i960
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
Ready/Receive Delay (CLK to RDYRCV)
Ready/Receive Delay to High Impedance
Write Data Setup Time
ADSN_SET
ADSN_HLD
RDYRCV_DEL
RDYRCV_DELZ
WD_SET
2.0
0.0
—
—
—
1.8
0.0
—
—
—
1.6
0.0
—
—
—
1.4
0.0
—
—
—
ns
ns
11.6
9.3
8.0
6.8 ns
(2)
(2)
(2)
(2)
—
—
—
—
ns
ns
ns
(3)
(3)
(3)
(3)
—
—
—
—
—
—
—
—
—
—
6.6
7.0
—
—
—
—
—
—
—
—
—
—
4.3
5.4
—
—
—
—
—
—
—
—
—
—
4.1
4.2
—
—
(4)
(4)
(4)
(4)
Write Data Hold Time
WD_HLD
A_SET
A_HLD
BE_SET
BE_HLD
RW_SET
RW_HLD
CS_SET
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
Read/Write Setup Time
2.0
2.0
2.0
1.8
1.8
1.8
0.50
0.51
0.50
—
—
—
0.42 ns
0.44 ns
0.42 ns
0.44 ns
—
—
2.0
1.8
0.51
—
(3)
(3)
(3)
(3)
ns
ns
(4)
(4)
(4)
(4)
Read/Write Hold Time
Chip Select Setup Time (CS0, CS1 to CLK)(1)
Chip Select Hold Time (CS0, CS1 from CLK)(1)
User Address Delay (CLK low to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
2.0
0.0
—
1.8
0.0
—
0.45
0.0
—
—
0.0
—
0.38 ns
ns
CS_HLD
UA_DEL
URDWR_DEL
—
3.5 ns
3.6 ns
—
—
—
—
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
Notes:
PowerPC i960
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (
,
) from the FPGA.
PowerPC i960
and
timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Lucent Technologies Inc.
115
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