Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 45.
Synchronous Memory Read Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Speed
Parameter
Unit
Symbol
-4
-5
-6
-7
J
DD
= min)
(T = 85 °C, V
Min Max Min Max Min Max Min Max
Read Operation:
Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0])
Data Valid After Address (F5[A:D] to F[6, 4, 2, 0])
RA_DEL
—
—
2.34
2.11
—
—
1.80
1.57
—
—
1.32
1.23
—
—
1.05 ns
0.99 ns
RA4_DEL
Read Operation, Clocking Data into Latch/FF:
Address to Clock Setup Time (Kz[3:0] to CLK)
Address to Clock Setup Time (F5[A:D] to CLK)
Address from Clock Hold Time (Kz[3:0] from CLK)
Address from Clock Hold Time (F5[A:D] from CLK)
Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0])
Read Cycle Delay
RA_SET
RA4_SET
RA_HLD
1.99
1.79
0.00
0.00
—
—
—
—
—
2.38
10.48
1.47
1.33
0.00
0.00
—
—
—
—
—
1.75
7.66
1.08
1.03
0.00
0.00
—
—
—
—
—
1.26
7.53
0.85
0.81
0.00
0.00
—
—
—
—
—
ns
ns
ns
ns
RA4_HLD
REG_DEL
SMRD_CYC
0.97 ns
5.78 ns
—
—
—
—
ORCA
Note: The table shows worst-case delays.
Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
Kz[3:0], F5[A:D]
RA_DEL
RA4_DEL
F[6, 4, 2, 0]
CLK
RA_HLD
RA4_HLD
RA_SET
RA4_SET
REG_DEL
SMRD_CYC
Q[3:0]
5-4622(F)
Figure 66. Synchronous Memory Read Cycle
110
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
