Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 44. Synchronous Memory Write Characteristics
DD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Cxx Commercial: V
OR3Txxx Commercial: V
DD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Unit
Parameter
Symbol
-4
-5
-6
-7
Min
Max
Min
Max
Min
Max
Min
Max
Write Operation for RAM Mode:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
SMCLK_FRQ
SMCLKL_MPW
SMCLKH_MPW
MEM_DEL
—
2.34
3.79
—
151.00
—
—
—
1.80
2.77
—
197.00
—
—
—
1.32
2.13
—
254.00
—
—
—
1.05
1.62
—
315.00 MHz
ns
ns
10.00
7.14
5.00
4.08
ns
Write Operation Setup Time:
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to
CLK)
WA4_SET
WA_SET
1.25
0.72
0.02
0.18
2.25
—
—
—
—
—
0.99
0.52
0.06
0.16
1.69
—
—
—
—
—
0.71
0.35
0.00
0.14
1.16
—
—
—
—
—
0.58
0.28
0.00
0.12
0.84
—
—
—
—
—
ns
ns
ns
ns
ns
WD_SET
WE_SET
WPE0_SET
Write-port Enable 1 (WPE1) to Clock (LSR to
CLK)
2.79
—
2.13
—
1.58
—
1.31
—
ns
WPE1_SET
Write Operation Hold Time:
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] from CLK)
Data from Clock (DIN[6, 4, 2, 0] from CLK)
Write Enable (WREN) from Clock (ASWE from
CLK)
WA4_HLD
WA_HLD
WD_HLD
WE_HLD
0.00
0.00
0.59
0.03
—
—
—
—
0.00
0.00
0.42
0.00
—
—
—
—
0.00
0.00
0.40
0.08
—
—
—
—
0.00
0.00
0.32
0.06
—
—
—
—
ns
ns
ns
ns
Write-port Enable 0 (WPE0) from Clock (CE
from CLK)
Write-port Enable 1 (WPE1) from Clock (LSR
from CLK)
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
WPE0_HLD
WPE1_HLD
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
ORCA
Note: The table shows worst-case delays.
Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
WA4_SET
WA_SET
WA4_HLD
WA_HLD
CIN, DIN[7, 5, 3, 1]
DIN[6, 4, 2, 0]
WD_SET
WD_HLD
WE_HLD
WE_SET
ASWE (WREN)
WPE0_HLD
WPE1_HLD
WPE0_SET
WPE1_SET
CE (WPE0),
LSR (WPE1)
TSCH
TSCL
CK
MEM_DEL
F[6, 4, 2, 0]
5-4621(F)
Figure 65.
Synchronous Memory Write Characteristics
Lucent Technologies Inc.
109
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