Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
PIO Timing
Table 48.
Programmable I/O (PIO) Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
Input Delays (TJ = 85 °C, VDD = min)
Input Rise Time
—
—
500
500
—
—
500
500
—
—
500
500
—
—
500
500
ns
ns
IN_RIS
IN_FAL
Input Fall Time
PIO Direct Delays:
—
—
—
1.41
2.16
9.05
—
—
—
1.26
1.87
7.83
—
—
—
0.64
1.28
6.64
—
—
—
0.41
0.90
7.27
ns
ns
ns
Pad to In (pad to CLK IN)
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
CKIN_DEL
IN_DEL
IND_DEL
PIO Transparent Latch Delays:
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
—
—
4.11
10.58
—
—
3.25
9.05
—
—
2.52
7.67
—
—
1.82
7.65
ns
ns
LATCH_DEL
LATCHD_DEL
Input Latch/FF Setup Timing:
Pad to ExpressCLK (fast-capture latch/FF)
Pad Delayed to ExpressCLK
INREGE_SET 5.93
INREGED_SET 12.86
4.82
11.03
3.63
9.18
3.23
9.68
—
—
—
—
—
—
—
—
ns
ns
(fast-capture latch/FF)
Pad to Clock (input latch/FF)
Pad Delayed to Clock (input latch/FF)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
INREG_SET
INREGD_SET 8.57
INCE_SET
INLSR_SET
1.62
1.42
7.36
1.64
1.45
0.71
5.91
1.29
1.14
0.50
7.06
1.00
0.89
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
2.03
1.79
Input FF/Latch Hold Timing:
INREGE_HLD 0.00
INREGED_HLD 0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
—
—
—
ns
ns
Pad from ExpressCLK (fast-capture latch/FF)
Pad Delayed from ExpressCLK
(fast-capture latch/FF)
Pad from Clock (input latch/FF)
Pad Delayed from Clock (input latch/FF)
Clock Enable from Clock (CE from CLK)
Local Set/Reset (sync) from Clock
(LSR from CLK)
INREG_HLD
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
INREGD_HLD 0.00
INCE_HLD
INLSR_HLD
0.00
0.00
INREG_DEL
INLTCH_DEL
INLSR_DEL
INLSRL_DEL
—
—
—
—
4.05
4.08
6.11
5.89
—
—
—
—
3.14
3.19
4.76
4.66
—
—
—
—
2.53
2.62
3.81
3.57
—
—
—
—
2.05
2.14
3.17
2.98
ns
ns
ns
ns
Clock-to-in Delay (FF CLK to IN1, IN2)
Clock-to-in Delay (latch CLK to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2)
LatchFF in Latch Mode
INGSR_DEL
—
5.38
—
4.22
—
3.44
—
2.88
ns
Global S/R to In (GSRN to IN1, IN2)
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.
112
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
