Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
UEND_SET
RDS_HLD
CS_SET
RW_SET
A_SET
CS_HLD
A_HLD
RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL
RDA_HLD
D[7:0]
MPI_STRB (TS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
USTARTCLR_DEL
USTART_DEL
USTART
USER LOGIC DELAY
UEND_DEL
TA_DEL
UEND
TA_DELZ
TA_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DEL
BI_DEL
BI_DELZ
5-5832(F)
Figure 67. MPI PowerPC User Space Read Timing
CS_SET
RW_SET
A_SET
WD_HLD
CS_HLD
RW_HLD
UEND_SET
A_HLD
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
WD_SET
D[7:0]
MPI_STRB (TS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
USTART
USTARTCLR_DEL
USTART_DEL
USER LOGIC DELAY
UEND_DEL
TA_DEL
UEND
TA_DELZ
TA_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DEL
BI_DEL
BI_DELZ
5-5840(F)
Figure 68. MPI PowerPC User Space Write Timing
Lucent Technologies Inc.
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