Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 42.
Sequential PFU Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
< TA <
VDD
< TA <
= 3.0 V to 3.6 V, –40 °C +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C
70 °C; Industrial:
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
Input Requirements
Clock Low Time
CLKL_MPW
CLKH_MPW
GSR_MPW
LSR_MPW
3.36
1.61
3.36
3.36
—
—
—
—
2.07
1.06
2.07
2.07
—
—
—
—
0.94
0.54
0.94
0.94
—
—
—
—
0.72
0.45
0.72
0.72
—
—
—
—
ns
ns
ns
ns
Clock High Time
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
J
DD
Combinatorial Setup Times (T = +85 °C, V = min):
Four-input Variables to Clock (Kz[3:0] to CLK)*
Five-input Variables to Clock (F5[A:D] to CLK)
Data In to Clock (DIN[7:0] to CLK)
F4_SET
F5_SET
1.99
1.79
0.47
1.25
2.86
1.68
1.86
1.37
3.98
4.06
6.49
6.39
—
—
—
—
—
—
—
—
—
—
—
—
1.47
1.33
0.32
0.99
2.15
1.30
1.36
1.00
2.99
2.97
4.81
4.73
—
—
—
—
—
—
—
—
—
—
—
—
1.08
1.03
0.18
0.71
1.80
0.95
0.86
0.92
2.13
2.29
3.42
3.34
—
—
—
—
—
—
—
—
—
—
—
—
0.85
0.81
0.16
0.58
1.37
0.77
0.68
0.70
1.63
1.68
2.64
2.57
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIN_SET
CINDIR_SET
CE1_SET
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK)
Clock Enable to Clock (CE to CLK)
Clock Enable to Clock (ASWE to CLK)
Local Set/Reset to Clock (SYNC) (LSR to CLK)
Data Select to Clock (SEL to CLK)
Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Two-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Three-level LUT to Clock (F5[A:D] to CLK w/feedbk)
CE2_SET
LSR_SET
SEL_SET
SWL2_SET
SWL2F5_SET
SWL3_SET
SWL3F5_SET
J
DD
Combinatorial Hold Times (T = all, V = all):
DIN_HLD
Data In (DIN[7:0] from CLK)
Carry-in from Clock, DIRECT to REGCOUT (CIN from
CLK)
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
CINDIR_HLD
CE1_HLD
CE2_HLD
LSR_HLD
SEL_HLD
—
Clock Enable (CE from CLK)
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
ns
ns
ns
ns
ns
Clock Enable from Clock (ASWE from CLK)
Local Set/Reset from Clock (sync) (LSR from CLK)
Data Select from Clock (SEL from CLK)
All Others
Output Characteristics
J
DD
Sequential Delays (T = +85 °C, V = min):
Local S/R (async) to PFU Out (LSR to Q[7:0], REG-
COUT)
LSR_DEL
—
7.02
—
5.29
—
3.64
—
2.90 ns
GSR_DEL
REG_DEL
Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT)
Clock to PFU Out—Register (CLK to Q[7:0], REG-
COUT)
—
—
5.21
2.38
—
—
3.90
1.75
—
—
2.55
1.26
—
—
2.00 ns
0.97 ns
LTCH_DEL
Clock to PFU Out—Latch (CLK to Q[7:0])
Transparent Latch (DIN[7:0] to Q[7:0])
—
—
2.51
2.73
—
—
1.88
2.10
—
—
1.21
1.38
—
—
0.96 ns
1.12 ns
LTCHD_DEL
* Four-input variables’ (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
ORCA
Note: The table shows worst-case delays.
Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
106
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
