Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 43. Ripple Mode PFU Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
VDD
< TA <
VDD
< TA <
+85 °C.
OR3Txxx Commercial:
= 3.0 V to 3.6 V, 0 °C
70 °C; Industrial:
= 3.0 V to 3.6 V, –40 °C
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
J
DD
(T = +85 °C, V = min)
Min Max Min Max Min Max Min Max
Full Ripple Setup Times (byte wide):
RIP_SET
FRIP_SET
FCIN_SET
CIN_SET
AS_SET
Operands to Clock (Kz[1:0] to CLK)
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CLK)
Add/Subtract to Clock (ASWE to CLK)
Operands to Clock (Kz[1:0] to CLK at REGCOUT)
Fast Carry-in to Clock (FCIN to CLK at REGCOUT)
Carry-in to Clock (CIN to CLK at REGCOUT)
Add/Subtract to Clock (ASWE to CLK at REGCOUT)
3.50
1.99
2.55
3.80
8.82
2.09
2.29
3.09
8.14
—
—
—
—
—
—
—
—
—
2.50
1.47
1.87
2.79
6.18
1.61
1.76
2.36
5.73
—
—
—
—
—
—
—
—
—
1.96
1.08
1.34
1.97
4.68
1.19
1.28
1.73
4.54
—
—
—
—
—
—
—
—
—
1.48
0.85
1.04
1.56
3.50
0.93
1.02
1.35
3.39
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
RIPRC_SET
FCINRC_SET
CINRC_SET
ASRC_SET
J
DD
Full Ripple Hold Times (T = all, V = all):
FCINRC_HLD
Fast Carry-in from Clock (FCIN from CLK at REG-
COUT)
All Others
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
GENERIC_HLD
Half Ripple Setup Times (nibble wide):
HRIP_SET
HFRIP_SET
HFCIN_SET
HCIN_SET
Operands to Clock (Kz[1:0] to CLK)
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CLK)
Add/Subtract to Clock (ASWE to CLK)
Operands to Clock (Kz[1:0] to CLK at REGCOUT)
Fast Carry-in to Clock (FCIN to CLK at REGCOUT)
Carry-in to Clock (CIN to CLK at REGCOUT)
Add/Subtract to Clock (ASWE to CLK at REGCOUT)
3.91
1.99
2.55
3.80
8.82
3.03
2.29
3.09
8.14
—
—
—
—
—
—
—
—
—
2.81
1.47
1.87
2.79
6.18
2.31
1.76
2.36
5.73
—
—
—
—
—
—
—
—
—
2.21
1.08
1.34
1.97
4.68
1.68
1.28
1.73
4.54
—
—
—
—
—
—
—
—
—
1.66
0.85
1.04
1.56
3.50
1.32
1.02
1.35
3.39
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
HAS_SET
HRIPRC_SET
HFCINRC_SET
HCINRC_SET
HASRC_SET
J
DD
Half Ripple Hold Times (T = all, V = all):
HFCINRC_HLD
GENERIC_HLD
Fast Carry-in from Clock (HFCIN from CLK at REG-
COUT)
All Others
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
ORCA
Note: The table shows worst-case delay for the ripple chain.
will be less than or equal to those listed above.
Foundry reports the delay for individual paths within the ripple chain that
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