Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Readback Timing
.
Table 66 Readback Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Parameter
Symbol
Min
50.00
2
Max
—
Unit
S
RD_CFG to CCLK Setup Time
RD_CFG High Width to Abort Readback
CCLK Low Time
T
ns
RBA
T
—
CCLK cycles
CL
T
40.00
40.00
—
—
ns
ns
CH
CCLK High Time
T
—
C
D
CCLK Frequency
F
12.50
40.00
MHz
ns
CCLK to RD_DATA Delay
T
—
TRBA
RD_CFG
TCL
TS
CCLK
TCH
TD
BIT 0
RD_DATA
BIT 0
BIT 1
5-4536(F)
Figure 88. Readback Timing Diagram
142
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
