tRC
Address
tAA
tOHA
Data Out
Previous Data Valid
Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE=LOW and OE=LOW
Figure 3a. Read Cycle 1
CE
tACE
OE
tHZCE
tHZOE
tDOE
tLZOE
tLZCE
Data Out
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Figure 3b. Read Cycle 2
tWC
Address
R/WR
MATCH
tPWE
tHD
tSD
DataINR
VALID
AddressL
MATCH
tDDD
VALID
DATAOUTL
tWDD
Assumptions:
1. BUSY = HIGH for the writing port
2. CE = CE = LOW
L
R
Figure 3c. Read Timing with Port-to-Port Delay
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