欢迎访问ic37.com |
会员登录 免费注册
发布采购

UT7C139C55WCA 参数 Datasheet PDF下载

UT7C139C55WCA图片预览
型号: UT7C139C55WCA
PDF下载: 下载PDF文件 查看货源
内容描述: 4Kx8 / 9抗辐射双口静态RAM与忙标志 [4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag]
分类和应用:
文件页数/大小: 21 页 / 360 K
品牌: AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
 浏览型号UT7C139C55WCA的Datasheet PDF文件第1页浏览型号UT7C139C55WCA的Datasheet PDF文件第2页浏览型号UT7C139C55WCA的Datasheet PDF文件第3页浏览型号UT7C139C55WCA的Datasheet PDF文件第5页浏览型号UT7C139C55WCA的Datasheet PDF文件第6页浏览型号UT7C139C55WCA的Datasheet PDF文件第7页浏览型号UT7C139C55WCA的Datasheet PDF文件第8页浏览型号UT7C139C55WCA的Datasheet PDF文件第9页  
The UT7C138/139 consists of an array of 4K words of 8 or 9  
bits of dual-port SRAM cells, I/O and address lines, and control  
signals (CE, OE, R/W). These control pins permit independent  
access for reads or writes to any location in memory. To handle  
simultaneous writes/reads to the same location, a BUSY pin is  
provided on each port. With the M/S pin, the UT7C138/139 can  
function as a master (BUSY pins are outputs) or as a slave  
(BUSY pins are inputs). Each port is provided with its own  
output enable control (OE), which allows data to be read from  
the device.  
input, the M/S pin allows the device to be used as a master and,  
therefore, the BUSY line is an output. BUSY can then be used  
to send the arbitration outcome to a slave. When presented as a  
LOW input, the M/S pin allows the device to be used as a slave,  
and, therefore, the BUSY pin is an input.  
Table 1. Non-Contending Read/Write  
INPUTS  
OUTPUTS  
CE  
H
R/W  
X
OE  
X
I/O0-7  
OPERATION  
WRITE CYCLE  
High Z  
High Z  
Power Down  
X
X
H
I/O Lines  
Disabled  
A combination of R/W less than VIL (max), andCE less than  
VIL (max), defines a write cycle. The state of OE is a “don’t  
care” for a write cycle. The outputs are placed in the high-  
impedance state when eitherOE is greater than VIH (min), or  
L
L
L
H
L
L
Data Out  
Data In  
---  
Read  
X
X
Write  
when R/W is less than VIL (max).  
X
Illegal  
Condition  
WRITE OPERATION  
Write Cycle 1, the Write Enable-controlled Access shown in  
figure 4a, is defined by a write terminated by R/W going high  
with CE active. The write pulse width is defined by tPWE when  
RADIATION HARDNESS  
the write is initiated by R/W, and by tSCE when the write is  
The UT7C138/139 incorporates special design and layout  
features which allow operation in high-level radiation  
environments. UTMC has developed special low-temperature  
processing techniques designed to enhance the total-dose  
radiation hardness of both the gate oxide and the field oxide  
while maintaining the circuit density and reliability. For  
transient radiation hardness and latchup immunity, UTMC  
builds all radiation-hardened products on epitaxial wafers using  
an advanced twin-tub CMOS process. In addition, UTMC pays  
special attention to power and ground distribution during the  
design phase, minimizing dose-rate upset caused by rail  
collapse.  
initiated byCE going active. Unless the outputs have been  
previously placed in the high-impedance state byOE, the user  
must wait tHZOE before applying data to the eight/nine  
bidirectional pins I/O(0:7/0:8) to avoid bus contention.  
Write Cycle 2, the Chip Enable-controlled Access shown in  
figure 4b, is defined by a write terminated byCE going inactive.  
The write pulse width is defined by tPWE when the write is  
initiated by R/W, and by tSCE when the write is initiated by CE  
going active. For the R/W initiated write, unless the outputs have  
been previously placed in the high-impedance state by OE, the  
user must wait tHZWE before applying data to the eight/nine  
bidirectional pins I/O(0:7/0:8) to avoid bus contention.  
Table 2. Radiation Hardness  
Design Specifications1  
If a location is being written by one port and the opposite port  
attempts to read that location, a port-to-port flow through delay  
must be met before the data is read on the output. Data will be  
valid on the port wishing to read the location (tBZA + t BDD) after  
Total Dose  
1.0E6  
85  
rads(Si)  
the data is written on the other port (see figure 5a).  
MeV-cm2/mg  
n/cm2  
LET Threshold  
READ OPERATION  
Neutron Fluence2  
3.0E14  
When reading the device, the user must assert both the OE and  
CE pins. Data will be available tACE after CE or tDOE afterOE  
< 1.376E -2 (4Kx8) cm2  
< 1.548E -2 (4Kx9)  
Memory Device  
Cross Section @ LET  
= 120MeV-cm2/mg  
is asserted (see figures 3a and 3b).  
MASTER/SLAVE  
A M/S pin is provided in order to expand the word width by  
configuring the device as either a master or a slave. The BUSY  
output of the master is connected to theBUSY input of the slave.  
Writing of slave devices must be delayed until after the BUSY  
input has settled. Otherwise, the slave chip may begin a write  
cycle during a contention situation. When presented as a HIGH  
Notes:  
1. The DPRAM will not latchup during radiation exposure under recommended  
operating conditions.  
2. Not tested for CMOS technology.  
4