AC CHARACTERISTICS BUSY CYCLE 1
(VDD = 5.0V±10%)
7C138 - 45
7C139 - 45
7C138 - 55
7C139 - 55
MIN MAX
SYMBOL
PARAMETER
UNIT
MIN
MAX
tBLA
tBZA
tBLC
tBZC
BUSY LOW from address match
BUSY HIGH-Z from address mismatch
BUSY LOW from CE LOW
25
25
25
25
30
ns
ns
ns
ns
ns
30
30
BUSY HIGH from CE HIGH
Port set-up for priority
30
2,3
5
5
tPS
tWB
tWH
tBDD
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to data valid
0
0
ns
ns
ns
40
50
45
55
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V /2, input pulse levels of 0.5V to V -0.5V, and output
DD
DD
loading of the specified I /I and 50-pF load capacitance.
OL OH
2. Violation of t (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
PS
3. When violating t , the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
PS
12
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
