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UT7C139C55WCA 参数 Datasheet PDF下载

UT7C139C55WCA图片预览
型号: UT7C139C55WCA
PDF下载: 下载PDF文件 查看货源
内容描述: 4Kx8 / 9抗辐射双口静态RAM与忙标志 [4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag]
分类和应用:
文件页数/大小: 21 页 / 360 K
品牌: AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
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tWC  
Address  
CE  
tSCE  
tAW  
tHA  
R/W  
tPWE  
tSD  
tHD  
tSA  
Data in  
DATA VALID  
tHZOE  
OE  
HIGH IMPEDANCE  
tLZOE  
Data out  
Assumptions:  
1. The internal write time of memory is defined by the overlap of CE  
LOW and R/W LOW. Both signals must be LOW to initiate a write,  
and either signal can terminate a write by going HIGH. The data input  
set-up and hold timing should be referenced to the rising edge of the  
signal that terminates the write.  
2. If OE is LOW during a R/W controlled write cycle, the write pulse  
width must be the larger of t  
or (t  
+ t ) to allow the I/O  
HZWE SD  
PWE  
drivers to turn off and data to be placed on the bus for the required t  
.
SD  
If OE is HIGH during a R/W controlled write cycle (as in this exam-  
ple), this requirement does not apply and the write pulse can be as  
short as the specified t  
.
PWE  
3. R/W must be HIGH during all address transactions.  
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)  
10