ADXL36±
Data Sheet
Table 10. SPI Timing (TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V)
Limit1, 2
Parameter
Min
Max
Unit
Description
1
MHz
Clock Frequency
fCLK
100
100
10
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Setup Time
CSS
tCSH
tCSD
tSU
CS Hold Time
CS Disable Time
Data Setup Time
Data Hold Time
tHD
tR
100
100
SCLK Rise Time
0
SCLK Fall Time
tF
100
100
100
100
0
Clock High Time
Clock Low Time
Clock Delay Time
Clock Enable Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
tHIGH
tLOW
tCLD
tCLE
tV
0
200
200
tHO
tDIS
0
1 Limits based on design targets; not production tested.
2 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
Rev. B | Page 22 of 44
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