Data Sheet
ADXL36±
SERIAL COMMUNICATIONS
The ADXL362 communicates via a 4-wire SPI and operates as a
slave. Ignore data that is transmitted from the ADXL362 to the
master device during writes to the ADXL362.
It is recommended that an even number of bytes be read (using
a multibyte transaction) because each sample consists of two
bytes: 2 bits of axis information and 14 bits of data. If an odd
number of bytes is read, it is assumed that the desired data was
read; therefore, the second half of the last sample is discarded so
a read from the FIFO always starts on a properly aligned even-
byte boundary. Data is presented least significant byte first,
followed by the most significant byte.
As shown in Figure 36 to Figure 40, the MISO pin is in a high
impedance state, held by a bus keeper, except when the ADXL362
is sending read data (to conserve bus power).
Wire the ADXL362 for SPI communication as shown in the
connection diagram in Figure 35. The recommended SPI clock
speeds are 1 MHz to 5 MHz, with 12 pF maximum loading.
MULTIBYTE TRANSFERS
Multibyte transfers, also known as burst transfers, are supported
for all SPI commands: register read, register write, and FIFO
read commands. It is recommended that data be read using
multibyte transfers to ensure that a concurrent and complete set
of x-, y-, and z-acceleration (and temperature, where applicable)
data is read.
The SPI timing scheme follows CPHA = CPOL = 0.
For correct operation of the part, the logic thresholds and timing
parameters in Table 9 and Table 10 must be met at all times.
Refer to Figure 41 and Figure 42 for visual diagrams of the
timing parameters.
PROCESSOR
ADXL362
The FIFO runs on the serial port clock during FIFO reads and
can sustain bursting at the SPI clock rate as long as the SPI clock
is 1 MHz or faster.
DOUT
DOUT
DIN
CS
MOSI
MISO
SCLK
Register Read/Write Auto-Increment
DOUT
A register read or write command begins with the address
specified in the command and auto-increments for each
additional byte in the transfer. To avoid address wrapping and
side effects of reading registers multiple times, the auto-
increment halts at the invalid Register Address 63 (0x3F).
Figure 35. 4-Wire SPI Connection Diagram
SPI COMMANDS
The SPI port uses a multibyte structure wherein the first byte is
a command. The ADXL362 command set is
INVALID ADDRESSES AND ADDRESS FOLDING
The ADXL362 has a 6-bit address bus, mapping only 64
registers in the possible 256 register address space. The
addresses do not fold to repeat the registers at addresses above
64. Attempted access to register addresses above 64 are mapped
to the invalid register at 63 (0x3F) and have no functional effect.
•
•
•
0x0A: write register
0x0B: read register
0x0D: read FIFO
Read and Write Register Commands
The command structure for the read register and write register
commands is as follows (see Figure 36 and Figure 37):
Address 0x00 to Address 0x2E are for customer access, as
described in the register map. Address 0x2F to Address 0x3F are
reserved for factory use.
</CS down> <command byte (0x0A or 0x0B)> <address
byte> <data byte> <additional data bytes for multi-byte> …
</CS up>
LATENCY RESTRICTIONS
Reading any of the data registers (0x08 to 0x0A or 0x0E to
0x15) clears the data ready interrupt. There can be as much as
an 80 µs delay from reading a register to the clearing of the data
ready interrupt.
The read and write register commands support multibyte
(burst) read/write access. The waveform diagrams for multi-
byte read and write commands are shown in Figure 38 and
Figure 39.
Other register reads, register writes, and FIFO reads have no
latency restrictions.
Read FIFO Command
Reading from the FIFO buffer is a command structure that does
not have an address.
INVALID COMMANDS
Commands other than 0x0A, 0x0B, and 0x0D have no effect.
The MISO output remains in a high impedance state, and the
bus keeper holds the MISO line at its last value.
</CS down> <command byte (0x0D)> <data byte> <data
byte> … </CS up>
Rev. B | Page 19 of 44
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