Data Sheet
ADXL36±
STATUS REGISTER
Address: 0x0B, Reset: 0x40, Name: STATUS
This register includes the following bits that describe various conditions of the ADXL362.
Table 12. Bit Descriptions for STATUS
Bits
Bit Name
Settings Description
Reset
Access
7
ERR_USER_REGS
SEU Error Detect. 1 indicates one of two conditions: either an SEU event,
0x0
R
such as an alpha particle of a power glitch, has disturbed a user register
setting or the ADXL362 is not configured. This bit is high upon both
startup and soft reset, and resets as soon as any register write commands
are performed.
6
AWAKE
Indicates whether the accelerometer is in an active (AWAKE = 1) or
inactive (AWAKE = 0) state, based on the activity and inactivity
functionality. To enable autosleep, activity and inactivity detection must
be in linked mode or loop mode (LINK/LOOP bits in the ACT_INACT_CTL
register); otherwise, this bit defaults to 1 and should be ignored.
0x1
R
5
4
3
INACT
Inactivity. 1 indicates that the inactivity detection function has detected
an inactivity or a free fall condition.
0x0
0x0
0x0
R
R
R
ACT
Activity. 1 indicates that the activity detection function has detected an
overthreshold condition.
FIFO_OVERRUN
FIFO Overrun. 1 indicates that the FIFO has overrun or overflowed, such
that new data replaces unread data. See the Using FIFO Interrupts
section for details.
2
FIFO_WATERMARK
FIFO Watermark. 1 indicates that the FIFO contains at least the desired
number of samples, as set in the FIFO_SAMPLES register. See the Using
FIFO Interrupts section for details.
0x0
R
1
0
FIFO_READY
DATA_READY
FIFO Ready. 1 indicates that there is at least one sample available in the
FIFO output buffer. See the Using FIFO Interrupts section for details.
0x0
0x0
R
R
Data Ready. 1 indicates that a new valid sample is available to be read.
This bit clears when a FIFO read is performed. See the Data Ready
Interrupt section for more details.
Rev. B | Page 25 of 44
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