Data Sheet
ADXL362
REGISTER MAP
Table 11. Register Summary
Reg Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DEVID_AD[7:0]
DEVID_MST[7:0]
PARTID[7:0]
REVID[7:0]
Bit 2
Bit 1
Bit 0
Reset RW
0xAD R
0x1D R
0x00 DEVID_AD
0x01 DEVID_MST
0x02 PARTID
0x03 REVID
[7:0]
[7:0]
[7:0]
0xF2
0x01
0x00
0x00
0x00
R
R
R
R
R
R
[7:0]
0x08 XDATA
0x09 YDATA
0x0A ZDATA
0x0B STATUS
[7:0]
XDATA[7:0]
YDATA[7:0]
ZDATA[7:0]
[7:0]
[7:0]
[7:0] ERR_USER_ AWAKE
REGS
INACT
ACT
FIFO_OVER- FIFO_WATER- FIFO_READY DATA_READY 0x40
RUN
MARK
0x0C FIFO_ENTRIES_L [7:0]
0x0D FIFO_ENTRIES_H [7:0]
FIFO_ENTRIES_L[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R
R
R
R
R
R
R
R
R
R
R
R
W
UNUSED
FIFO_ENTRIES_H[1:0]
XDATA_H[3:0]
0x0E XDATA_L
0x0F XDATA_H
0x10 YDATA_L
0x11 YDATA_H
0x12 ZDATA_L
0x13 ZDATA_H
0x14 TEMP_L
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
XDATA_L[7:0]
YDATA_L[7:0]
ZDATA_L[7:0]
TEMP_L[7:0]
SX
SX
SX
SX
YDATA_H[3:0]
ZDATA_H[3:0]
TEMP_H[3:0]
0x15 TEMP_H
0x16 Reserved
0x17 Reserved
0x1F SOFT_RESET
0x20 THRESH_ACT_L
Reserved[7:0]
Reserved[7:0]
SOFT_RESET[7:0]
THRESH_ACT_L[7:0]
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x80 RW
0x21 THRESH_ACT_H [7:0]
0x22 TIME_ACT [7:0]
UNUSED
UNUSED
THRESH_ACT_H[2:0]
TIME_ACT[7:0]
0x23 THRESH_INACT_L [7:0]
0x24 THRESH_INACT_H [7:0]
THRESH_INACT_L[7:0]
THRESH_INACT_H[2:0]
0x25 TIME_INACT_L
0x26 TIME_INACT_H
[7:0]
[7:0]
TIME_INACT_L[7:0]
TIME_INACT_H[7:0]
0x27 ACT_INACT_CTL [7:0]
RES
LINKLOOP
INACT_REF
AH
INACT_EN
ACT_REF
ACT_EN
0x28 FIFO_CONTROL
0x29 FIFO_SAMPLES
0x2A INTMAP1
[7:0]
UNUSED
INACT
FIFO_TEMP
FIFO_MODE
[7:0]
FIFO_SAMPLES[7:0]
[7:0] INT_LOW
AWAKE
AWAKE
ACT
FIFO_OVER- FIFO_WATER- FIFO_READY DATA_READY 0x00 RW
RUN MARK
FIFO_OVER- FIFO_WATER- FIFO_READY DATA_READY 0x00 RW
0x2B INTMAP2
[7:0] INT_LOW
INACT
RES
ACT
RUN
MARK
0x2C FILTER_CTL
0x2D POWER_CTL
0x2E SELF_TEST
[7:0]
RANGE
EXT_CLK
HALF_BW
EXT_SAMPLE
WAKEUP
ODR
0x13 RW
0x00 RW
0x00 RW
[7:0] RES
[7:0]
LOW_NOISE
UNUSED
AUTOSLEEP
MEASURE
ST
Rev. B | Page 23 of 44
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