AD5940
Data Sheet
SPI INTERFACE
OVERVIEW
COMMAND BYTE
The AD5940 provides an SPI interface to facilitate configuration
and control by a host microcontroller. The host controller uses
the SPI to read from and write to memory, registers, and FIFOs.
The AD5940 operate as a slave SPI device.
The first byte sent from the host to the AD5940 in an SPI
transaction is the command byte. The command byte specifies
the SPI protocol used for the SPI transaction. The available
commands are detailed in Table 125.
SPI PINS
Table 125. SPI Commands
CS
Command
Value Description
The SPI connections between the host and the AD5940 are
SCLK, MOSI, and MISO.
,
SPICMD_SETADDR
0x20
Set register address for SPI
transaction
Chip Select Enable
SPICMD_READREG
0x6D
Specifies SPI transaction is a read
transaction
CS
The host must connect the SPI slave enable signal to the
input
of the AD5940. To initiate an SPI transaction, the host drives
SPICMD_WRITEREG 0x2D
SPICMD_READFIFO 0x5F
Specifies SPI transaction is a write
transaction
Command to read FIFO
CS
the
signal low before the first SCLK rising edge and drives it
high again after the last SCLK falling edge. The AD5940 ignores
CS
the SCLK and MOSI signals of the SPI when the input is high.
Two main SPI transaction protocols are available on the
AD5940: writing to and reading from registers and reading data
from the data FIFO.
SCLK
SCLK is the serial clock driven by the host to the AD5940. The
maximum clock speed is 16 MHz.
WRITING TO AND READING FROM REGISTERS
Writing to and reading from a register requires two SPI
transactions. The first transaction sets the register address. The
second transaction is the actual read or write to the required
register. The following are the steps to write to a register:
MOSI and MISO
MOSI is the data input line driven from the host to the AD5940,
and MISO is the data output from the AD5940 to the host. The
MOSI signal and MISO signal are launched on the falling edge of
the SCLK signal and sampled on the rising edge of the SCLK
signal by the host and the AD5940, respectively. The MOSI
signal carries the data from the host to the AD5940. The MISO
signal carries the returning read data fields from the AD5940 to
the host during a read transaction.
1. Write the command byte and configure the register
address.
CS
a. Drive
low.
b. Send 8-bit command byte: SPICMD_SETADDR.
c. Send 16-bit address of register to read to or write
from.
SPI OPERATION
CS
d. Pull
2. Write the data to the register.
CS
high.
The host is the master of the SPI. The features and requirements
of SPI operation are as follows:
a. Drive
low.
•
SCLK is always slower than the system clock on the AD5940,
which is 16 MHz.
b. Send 8-bit command byte: SPICMD_WRITEREG.
c. Write either 16-bit or 32-bit data to the register.
CS
CS
•
When the
signal is brought low, a multiple of eight
d. Bring
3. Read the data from the register.
CS
high.
clock cycles must be generated by the host.
Transfers over the SPI slave are always byte aligned.
In every octet, the most significant bit (Bit 7) is transmitted
and received first.
If the signal is brought high at any time by the host, the
AD5940 is ready to accept new SPI transactions when the
a. Drive
low.
•
•
b. Send 8-bit command byte: SPICMD_READREG.
c. Transmit a dummy byte on the SPI bus to initiate a
read.
CS
•
d. Read returning 16-bit or 32-bit data.
CS
e. Bring
high.
CS
signal is brought low again by the host. The minimum
CS
time between
Table 4).
going high and going low again is t10 (see
Rev. 0 | Page 96 of 130
ADI [ ADI ]
