AD5940
Data Sheet
V
ZERO
R
LPF
+
0xFFFF
0xC000
R
LOAD
LPTIA
–
SE0
R
TIA
0x8000
AIN4/
LPF0
Figure 30. Low Power TIA Current Input Channel to the ADC
0x4000
0x0000
SELECTING INPUTS TO ADC MUX
For optimum ADC operation, the following are the
recommended mux inputs based on measurement type:
0.2V
1.1V
2.0V
Figure 29. Ideal ADC Transfer Function, Output Codes vs. Voltage Input
Voltage measurement
Calculate the input voltage, VIN, with the following equation:
Positive mux select = CE0, RE0, SE0, DE0, and AINx
Negative mux select = VBIAS_CAP pin
DC current measurement on low power TIA
Positive mux select = low-pass filter of low power TIA
Negative mux select =LPTIA_N node
AC or higher bandwidth current measurements on the low
power TIA
Positive mux select = LPTIA_P node
MUXSEL_N = LPTIA_N node
Current and impedance measurement on the high speed TIA
1.835 V
PGA _G
ADCDAT 0x8000
VIN =
VBIAS _CAP
215
where:
PGA_G is the PGA gain and is selectable as 1, 1.5, 2, 4, or 9.
ADCDAT is the raw ADC code in the ADCDAT register.
VBIAS_CAP is the voltage of the VBIAS_CAP pin, typically
1.11 V.
ADC LOW POWER CURRENT INPUT CHANNEL
Figure 30 shows the low power TIA input current channel. The
ADC measures the output voltage of the low power TIA.
MUXSEL_P = positive high speed TIA input
MUXSEL_N = negative high speed TIA input
The positive inputs can be selected via ADCCON, Bits[5:0].
The negative input is nominally selected to be the 1.11 V
reference source. Perform this selection by setting ADCCON,
Bits[12:8] = 01000 for VBIAS_CAP.
ADC POSTPROCESSING
The AD5940 provides many digital filtering and averaging
options to improve signal-to-noise performance and overall
measurement accuracy. Figure 31 shows an overview of the
postprocessing filter options.
An optional programmable gain stage can be selected to amplify
the positive voltage input. The instrumentation amplifier is
enabled via AFECON, Bit 10. The gain setting is configured via
ADCCON, Bits[18:16].
The processing filter options include the following:
Digital filtering (sinc2 or sinc3) and 50 Hz or 60 Hz power
supply rejection.
The output of the gain stage goes through an antialias filter. The
cutoff frequency of the antialias filter is set by PMBW, Bits[3:2].
Set the cutoff frequency to suit the input signal bandwidth.
DFT used with impedance measurements to automatically
calculate magnitude and phase values.
Programmable averaging of ADC results.
Programmable statistics option for calculating mean and
variance automatically.
The ADC output code is calibrated with an offset and gain
correction factor. This digital adjustment factor occurs
automatically. The offset and gain correction register used
depends on the ADC input channel selected.
Sinc3 Filter
See the Low Power TIA section for details on how to configure
the RLOAD, RTIA, and RFILTER resistor values. The low power TIA
output has a low-pass filter consisting of RFILTER and an external
capacitor connected to the AIN4/LPF0 pin. RFILTER is typically
1 MΩ and the external capacitor is recommended to be 1 μF,
which provides a low cutoff frequency.
The input to the sinc3 filter is the raw ADC codes at a rate of
800 kHz (if the 16 MHz oscillator is selected) or 1.6 MHz (if the
32 MHz oscillator is selected). To enable the sinc3 filter, ensure that
ADCFILTERCON, Bit 6 = 0. The filter decimation rate is
programmable with options of 2, 4, or 5. It is recommended to
use a decimation rate of 4.
The gain correction block is enabled by default and is not user
programmable.
Rev. 0 | Page 52 of 130
ADI [ ADI ]
