Data Sheet
AD5940
To support a range of current and voltage based input ranges,
the ADC front end provides a PGA and a TIA. The PGA
supports gains of 1, 1.5, 2, 4, and 9. The low power TIA supports
programmable gain resistors ranging from 200 Ω to 512 kΩ.
The high speed TIA used for impedance measurement supports
programmable gain resistors ranging from 200 Ω to 160 kΩ.
ADC CIRCUIT FEATURES
An input multiplexer, located in front of the high speed,
multichannel, 16-bit ADC, enables the measurement of a
number of external and internal channels. These channels
include the following:
•
Two low power current measurement channels. These
channels measure the low current outputs of the connected
sensor through the SE0 pin or DE0 pin. The current
channels feed into a programmable load resistor.
One low power TIA. The low power TIA has its own
programmable gain resistor to convert very small currents
to a voltage signal that can be measured by the ADC. The
low power current channel can be configured to sample
with or without a low-pass filter in place.
By default, the reference source of the ADC is a precision, low
drift, internal 1.82 V reference source. Optionally, an external
reference can be connected to the VREF_1.82V pin and the
AGND_REF pin.
•
The ADC supports averaging and digital filtering options. The
user can trade off speed vs. precision by using these options.
The highest ADC update rate is 800 kHz in normal mode and
1.6 MHz in high speed mode, with no digital filtering. The
ADC filtering options also include a 50 Hz/60 Hz mains power
supply filter. With this filter enabled, the ADC update rate is
typically 900 Hz.
•
•
One high speed current input channel for performing
impedance measurements up to 200 kHz. The high speed
current channel has a dedicated high speed TIA with a
programmable gain resistor.
The ADC supports a number of post processing features, including
a DFT engine intended for impedance measurements to remove
the processing requirements from the host microcontroller.
Minimum, maximum, and mean value detection is also supported.
Multiple external voltage inputs.
•
Six dedicated voltage input channels: AIN0, AIN1,
AIN2, AIN3/BUF_VREF1V8, AIN4/LPF0, and AIN6.
The sensor electrode pins, SE0, DE0, RE0, and CE0,
can also be measured as ADC voltage pins. Divide by
2 options are available on the CE0 pin.
•
ADC CIRCUIT OPERATION
The SAR ADC is based on a charge redistribution DAC. The
capacitive DAC consists of two identical arrays of 16 binary
weighted capacitors that are connected to the two inputs of the
comparator.
•
•
Internal ADC channels.
•
AVDD, DVDD, and AVDD_REG power supply
measurement channels.
The ADC block operates from the 16 MHz clock in normal
operation and samples at 800 kSPS. The postprocessing sinc3 and
sinc2 filters reduce this output sampling rate. It is recommended to
use a sinc3 oversampling rate of 4, which gives an output data
rate of 200 kSPS.
•
ADC, high speed DAC, and low power reference
voltage sources.
•
•
Internal die temperature sensor.
Two low power DAC output voltages, VBIAS0 and
VZERO0
.
For high power mode, the 32 MHz oscillator must be selected as
the ADC clock source. The ADC maximum update rate is
1.6 MSPS with higher power consumption, which is only
required for impedance measurements in the >80 kHz range.
ADC result post processing features.
•
•
Digital filters (sinc2 and sinc3) and 50 Hz/60 Hz
power supply rejection. The sinc2 and sinc3 filters
have programmable oversampling rates to allow the
user to trade off conversion speed vs. noise
performance.
Discrete Fourier transform (DFT), used with
impedance measurements to automatically calculate
magnitude and phase values.
ADC TRANSFER FUNCTION
The transfer function in Figure 29 shows the ADC output codes
on the y-axis vs. the differential voltage into the ADC.
In Figure 29, the ADC negative input channel is the 1.11 V
voltage source.
•
•
Programmable averaging of ADC results to separate
the sinc2 and sinc3 filters.
Programmable statistics option for calculating mean
and variance automatically.
The positive input channel is any voltage input to the ADC after
the TIA or PGA and/or input buffer stages.
•
Multiple calibration options to support system calibration
of the current, voltage, and temperature channels.
The ADC input stage provides an input buffer to support low
input current leakage specifications on all channels.
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