AD5940
Data Sheet
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Offset Error Drift
Gain = 2
Gain = 0.05
DC PSRR
40
5
70
μV/°C
μV/°C
dB
DC variation due to AVDD supply changes
PGA, Programmable Gain
0.05
2
Gain
Reconstruction Filter
3 dB Corner Frequency Accuracy
Allowed External Load Capacitance
<80 kHz (Low Power Mode)
>80 kHz (High Power Mode)
Overcurrent Limit Protection1
5
%
Programmable to 50 kHz, 100 kHz, and 250 kHz
SE0, DE0, AINx, and RCAL0/RCAL1 pins
100
80
pF
pF
mA
15
Amplifier attempts to limit the source/sink
current to this value via the internal clamp
Allowed Duration of Overcurrent
Limit1
Allowed Frequency of Overcurrent
Conditions1
5
1
sec
Per hour
mA
Short-Circuit Protection
10
When amplifier output is shorted to ground
Switches on analog front end before ADC mux
Characterized with a voltage sweep from 0 V to
AVDD; production tested at 1.82 V
SWITCH MATRIX
On Resistance1
RON
Current Carrying Switches
40
30
35
1
370
530
80
52
70
5
Ω
Ω
Ω
kΩ
pA
pA
Tx/TR1 switches, except T5 and T7
T5 and T7 switches only
Dx/DR0 switches
Nx/Nxx and Px/Pxx switches
Analog input pin used for test driven to 0.2 V
Analog input pin used for test driven to 0.2 V
Noncurrent Carrying Switches
DC Off Leakage
DC On Leakage1
2000
TEMPERATURE SENSOR
Resolution
Accuracy
0.3
2
°C
°C
Measurement taken immediately after exiting
hibernate mode; user single-point calibration
required
POWER-ON RESET
POR Trip Level
Power-On
Power-Down1
POR Hysteresis1
POR
Refers to voltage on DVDD pin
1.59
1.799
1.62
1.8
10
1.72
1.801
V
V
mV
ms
Delay Between POR Power-On and
Power-Down Trip Levels1
110
1
After DVDD passes POR power-on trip level,
DVDD must remain at or above power-down
level for this period
External Reset
Minimum Pulse Width1
μs
Minimum pulse width required on external
reset pin to trigger a reset
WAKE-UP TIMER
Shortest Duration
Longest Duration
DIGITAL INPUTS
Input Leakage Current1
Logic 1 GPIO
31.25
32
μs
sec
1
5
nA
nA
pF
Voltage input high (VIH ) = IOVDD, pull-up resistor
disabled
Voltage input low (VIL ) = 0 V, pull-up resistor
disabled
Logic 0 GPIO
1
10
Input Capacitance
Pin Capacitance
XTALI
10
10
10
pF
pF
XTALO
Rev. 0 | Page 12 of 130
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