Data Sheet
AD5940
Parameter
Differential Offset VBIAS0 to VZERO0 ≈ 0 V1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
4
μV/°C
Differential offset voltage of VBIAS0 referred to
VZERO0; −40°C to +60°C range; LPDACDAT0 =
0x1A680
Differential Offset VBIAS0 to VZERO0
±600 mV1
≈
10
μV/°C
Differential offset voltage of VBIAS0 referred to
VZERO0, −40°C to +60°C range; LPDACDAT0 =
0x1AAE0
12-bit mode, DAC code = 0xFFF with target
voltage of 2.4 V
Gain Error1
±0.2
10
±0.5
%
Drift
ppm/°C
Using internal low power reference
Analog Outputs
Output Voltage Range1
LSB size = 2.2/(212 − 1); the input common-
mode voltage of the low power potentiostat
amplifier and low power TIA = AVDD – 600 mV
12-Bit Outputs
6-Bit Outputs
0.2
2.4
V
AVDD ≥ 2.8 V
LSB size is 2.2/26; the input common-mode
voltage of the low power potentiostat amplifier
and low power TIA = AVDD – 600 mV
0.2
0.2
400
2.366
2.3
V
V
mV
AVDD ≥ 2.8 V
AVDD < 2.8V
A minimum headroom between AVDD and
VBIAS0/VZERO0 output voltage, increases to 600 mV
if connected to low power TIA or low power
low power potentiostat amplifiers
AVDD to VBIAS0/VZERO0 Headroom Voltage1
Output Impedance1
DAC AC Characteristics
Output Settling Time
1.65
1.5
MΩ
sec
Settled to ±2 LSB12 with 0.1 μF load for ¼ of full
scale to ¾ of full scale
Output Settling Time
Glitch Energy
500
±5
μs
nV/sec
Settled to ±2 LSB12; no load
1 LSB change when the maximum number of
bits changes simultaneously in the LPDACDAT0
register; switch to external capacitors on
VBIAS0/VZERO0 opened; no capacitors on CE0 and
RC0_x pins
EXCITATION DAC/PGA/
RECONSTRUCTION FILTER
Use HSDACDAT register range of 0x200 to
0xE00; specified for gain = 2 (HSDACCON, Bit 12
and Bit 0 = 0); for gain =0.05 (HSDACCON,
Bit 12 and Bit 0 = 1)
DAC
Common-Mode Voltage Range1
0.2
12
AVDD
− 0.6
V
Set by the negative node of the excitation
amplifier
1 LSB = 293 μV × programmable gain
Gain = 2
Gain = 0.05
Gain = 2
Resolution1
Differential Nonlinearity1
Bits
LSB
LSB
LSB
LSB
LSB
DNL
INL
−0.99
+1.25
±20
±3
±20
±3
±±
±2
±8
±0.6
Integral Nonlinearity1
Gain = 0.05
Gain = 2
Full-Scale Error1, ±
Positive
600
630
15.1
−640
−15.1
650
mV
mV
mV
mV
Gain = 2, DAC code = 0xE00
Gain = 0.05, DAC code = 0xE00
Gain = 2, DAC code = 0x200
Gain = 0.05, DAC code = 0x200
Negative
−660
−620
Gain Error Drift
Gain = 2
Gain = 0.05
11.5
0.33
μV/°C
μV/°C
Offset Error (Midscale)
Measured at an output of the excitation loop
across RCAL; DAC code = 0x800
±25
±0.5
mV
mV
Gain = 2
Gain = 0.05
Rev. 0 | Page 11 of 130
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