AD±±70
V
AD5570 to MC68HC11 Interface
LOGIC
AD5570*
8xC51*
Figure ꢁ1 shows an example of a serial interface between the
AD5570 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL = 0), and
the clock phase bit (CPHA = 1). The SPI is configured by
writing to the SPI control register (SPCR)—see the 68HC11
User Manual. SCK of the 68HC11 drives the SCLK of the
AD5570, the MOSI output drives the serial data line (DIN) of
the AD5570, and the MISO input is driven from SDO. The
RxD
SDO
DIN
TxD
SCLK
P3.3
P3.4
SYNC
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
is driven from one of the port lines, in this case PC7.
SYNC
Figure 42. AD5570 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between this DAC and the microcontroller
interface.
When data is being transmitted to the AD5570, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 16-bit word, PC7 is not brought high
until the second 8-bit word has been transferred to the DAC’s
input shift register.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the second byte has been
transferred, the P3.3 line is taken high. The DAC may be
MC68HC11*
AD5570*
MISO
SDO
updated using
via P3.ꢁ of the 8051.
LDAC
MOSI
SCLK
PC7
DIN
AD5570 to ADSP2101/ADSP2103
SCLK
An interface between the AD5570 and the ADSPꢀ101/
ADSPꢀ103 is shown in Figure ꢁ3. The ADSPꢀ101/ADSPꢀ103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSPꢀ101/ADSPꢀ103 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length.
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5570 to MC68HC11 Interface
is controlled by the PC6 port output. The DAC can be
LDAC
updated after each ꢀ-byte transfer by bringing
low. This
LDAC
example does not show other serial lines for the DAC. If
were used, it could be controlled by port output PC5, for
example.
CLR
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
AD5570 to 8051 Interface
output is updated using the
pin via the DSP. Alterna-
LDAC
The AD5570 requires a clock synchronized to the serial data.
For this reason, the 8051 must be operated in Mode 0. In this
mode, serial data enters and exits through RxD, and a shift clock
is output on RxD.
tively, the
input could be tied permanently low, and then
LDAC
the update takes place automatically when
is taken high.
TFS
ADSP2101/
ADSP2103*
AD5570*
P3.3 and P3.ꢁ are bit programmable pins on the serial port and
DR
SDO
are used to drive
and
, respectively.
SYNC
LDAC
DT
DIN
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user must ensure that the data in the SBUF
register is arranged correctly, because the DAC expects MSB
first.
SCLK
SCLK
TFS
SYNC
LDAC
RFS
FO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. AD5570 to ADSP2101/ADSP2103 Interface
Rev. 0 | Page 21 of 24
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