AD±±70
GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 11.ꢁ V to 16.5 V, and has a
buffered voltage output of up to 13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy
chaining or readback.
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure ꢀ.
The AD5570 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V. The device also
has a power-down pin, which reduces the typical current
consumption to 16 µA.
Upon power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of −ꢀ VREF; all 1s produce an
output of +ꢀ VREF − 1 LSB.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit
current-mode segmented R-ꢀR DAC. The simplified circuit
diagram for the DAC section is shown in Figure 35.
The
input is a level-triggered input that acts as a frame
SYNC
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
the 15 matched resistors to either AGND or IOUT. The remain-
ing 1ꢀ bits of the data word drive switches S0 to S11 of the
1ꢀ-bit R-ꢀR ladder network.
synchronization signal and chip enable.
must frame the
SYNC
serial word being loaded into the device. Data can be trans-
ferred into the device only while is low. To start the serial
SYNC
should be taken low, observing the
data transfer,
SYNC
to SCLK falling edge setup time, tꢁ. After
minimum
SYNC
R
R
R
goes low, serial data on SDIN is shifted into the device’s
SYNC
input shift register on the falling edges of SCLK.
taken high after the falling edge of the 16th SCLK pulse,
V
ref
may be
SYNC
2R
2R
2R
2R
2R
2R
2R
observing the minimum SCLK falling edge to
time, t7.
rising edge
SYNC
R/8
E15
E14
E1
S0
S11
S10
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register of
the DAC.
V
OUT
AGND
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12 BIT R-2R LADDER
When data has been transferred into the input register of the
DAC, the DAC register and DAC output can be updated by
taking LDAC low while SYNC is high.
Figure 35. DAC Ladder Structure
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input
voltage is then used to provide a buffered positive and negative
reference for the DAC core. The positive reference is given by
LDAC
Load DAC Input (
)
When data has been transferred into the input register of the
DAC, there are two ways in which the DAC register and DAC
output can be updated. Depending on the status of both
SYNC
+ VREF = 2 ×VREFIN
and
, one of two update modes is selected.
LDAC
while the negative reference to the DAC core is given by
LDAC
Synchronous
being clocked into the input shift register. The DAC output is
updated when is taken high. The update here occurs on
: In this mode,
is low while data is
LDAC
−VREF = 2 ×VREFIN
SYNC
the rising edge of
.
SYNC
These positive and negative reference voltages define the DAC
output range.
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