AD±±70
68HC11*
MOSI
AD5570*
SERIAL DATA OUTPUT (SDO)
SDIN
The serial data output (SDO) is the internal shift register’s
output. For the AD5570, SDO is an internal pull-down only; an
external pull-up resistor of ~5 kΩ to external logic high is
required. SDO pull-down is disabled when the device is in
power-down, thus saving current.
SCK
PC7
PC6
SCLK
SYNC
LDAC
V
LOGIC
MISO
SDO
R
R
R
The availability of SDO allows any number of AD5570s to be
daisy-chained together. It also allows for the contents of the
DAC register, or any number of DACs daisy-chained together,
to be read back for diagnostic purposes.
SDIN
AD5570*
SCLK
SYNC
LDAC
Daisy Chaining
This mode of operation is designed for multi-DAC systems,
where several AD5570s may be connected in cascade as shown
in Figure 37. This is done by connecting the control inputs in
parallel and then daisy chaining the SDIN and SDO I/Os of
each device. An external pull-up resistor of ~5 kΩ on SDO is
required when using the part in daisy-chain mode.
SDO
SDIN
AD5570*
SCLK
SYNC
LDAC
As before, when
goes low, serial data on SDIN is shifted
SYNC
into the input shift register on the falling edge of SCLK. If more
than 16 clock pulses are applied, the data ripples out of the shift
resister and appears on the SDO line. By connecting this line to
the SDIN input on the next AD5570 in the chain, a multi-DAC
interface may be constructed.
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. Daisy Chaining Using the AD5570
One data transfer cycle of 16 SCLK pulses is required for each
DAC in the system. Therefore, the total number of clock cycles
must equal 16 N, where N is the total number of devices in the
chain. The first data transfer cycle written into the chain
appears at the last DAC in the system on the final data transfer
cycle.
Readback
The AD5570 allows the data contained in the DAC register to
be read back, if required. As with daisy chaining, an external
pull-up resistor of ~5 kΩ on SDO is required. The data in the
DAC register is available on SDO on the falling edges of SCLK
when
is low. On the sixteenth SCLK edge, SDO is
SYNC
updated to repeat SDIN with a delay of 16 clock cycles.
When the serial transfer to all devices is complete,
should
SYNC
be taken high. This prevents any further data from being
clocked into the devices.
To read back the contents of the DAC register without writing
to the part,
should be taken low while LDAC is held high.
SYNC
A continuous SCLK source may be used, if it can be arranged
that is held low for the correct number of clock cycles.
Daisy-chaining readback is also possible through the SDO pin
of the last device in the DAC chain, because the DAC data
passes through the DAC chain with the appropriate latency.
SYNC
Alternatively, a burst clock containing the exact number of
clock cycles may be used and taken high some time later.
SYNC
The outputs of all the DACs in the system can be updated
simultaneously using the signal.
LDAC
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