AD±±70
LDAC
CLEAR (CLR)
Asynchronous
: In this mode,
is high while data is
LDAC
being clocked in. The DAC output is updated by taking
LDAC
has been taken high. The update now
is an active low digital input that allows the output to be
CLR
low any time after
SYNC
cleared to 0 V. When the
output stays at 0 V until
signal is brought back high, the
CLR
occurs on the falling edge of
.
LDAC
is brought low. The relationship
LDAC
between
and
is explained further in Table 7.
CLR
LDAC
Figure 36 shows a simplified block diagram of the input loading
circuitry.
Table 7. Relationships among
,
, and
LDAC
PD CLR
PD CLR LDAC Comments
OUTPUT
I/V AMPLIFIER
0
1
x
x
PD has priority over LDAC and CLR. The
output remains at 0 V through an internal
20 kΩ resistor. It is still possible to address
both the input register and DAC register
when the AD55±0 is in power-down.
Data is written to the input register and
DAC register. CLR has higher priority over
LDACꢂ therefore, the output is at 0 V.
16-BIT
DAC
V
REFIN
V
OUT
LDAC
SYNC
DAC
REGISTER
0
0
INPUT SHIFT
REGISTER
SDIN
SDO
1
1
1
0
1
1
1
0
1
Data is written to the input register only.
The output is at 0 V and remains at 0 V,
when CLR is taken back high.
Figure 36. Simplified Serial Interface Showing Input Loading Circuitry
Data is written to the input register and
the DAC register. The output is driven to
the DAC level.
Data is written to the input register only.
The output of the DAC register is
unchanged.
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage relationship
for the AD5570.
Table 6. Binary Code Table
Digital Input
Analog Output
MSB
1111
1000
1000
0111
0000
LSB
VOUT
POWER-DOWN (PD)
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREF × (32,±6±/32,±6ꢁ)
+2 VREF × (1/32,±6ꢁ)
0 V
−2 VREF × (1/32,±6ꢁ)
−2 VREF
The power-down pin allows the user to place the AD5570 into a
power-down mode. When in this mode, power consumption is
at a minimum; the device consumes only 16 µA typically.
POWER-ON RESET
The AD5570 contains a power-on reset circuit that controls the
output during power-up and power-down. This is useful in
applications where the known state of the output of the DAC
during power-up is important. On power-up and power-down,
the output of the DAC, VOUT, is held at AGND.
The output voltage expression is given by
VOUT = −ꢀVREFIN + ꢁ × VREFIN [D / 65536]
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN is the reference voltage available at the REFIN pin.
Rev. 0 | Page 1± of 24
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