AD±±70
0
–1
–2
11.0
10.0
REFIN = 5V
8.0
V
/V = ±15V
DD SS
6.0
4.0
–3
–4
–5
2.0
V
/V = ±12V
DD SS
0
–6
–7
–8
–9
–2.0
–4.0
1µs/DIV
V
V
= +15V
= –15V
DD
–6.0
–8.0
SS
REFIN = 5V
= 25°C
T
A
–10.0
–10
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 24. Bipolar Zero Error vs. Temperature
Figure 27. Settling Time
40
10
0
REFIN = 5V
T
= 25°C
A
REFIN = 5V
35
30
6
V
/V = ±12V
DD SS
4
2
0
25
V
/V = ±15V
DD SS
20
15
10
5
V
/V = ±15V
DD SS
–2
–4
–6
–8
V
/V = ±12V
DD SS
0
–10
–40
0
1
2
3
4
5
6
7
8
9 9.4
–20
0
20
40
60
80
100
120
CAPACITANCE (nF)
TEMPERATURE (°C)
Figure 25. Gain Error vs. Temperature
Figure 28.14-Bit Settling Time vs. Load Capacitance
4.15
10.0000
9.9997
T
= 25°C
T
= 25°C
A
A
REFIN = 5V
REFIN = 5V
4.10
4.05
9.9994
9.9991
9.9988
9.9985
15V SUPPLIES
DECREASING
4.00
3.95
9.9982
9.9979
15V SUPPLIES
INCREASING
9.9976
9.9973
9.9970
9.9967
9.9964
9.9961
DECREASING
INCREASING
3.90
3.85
3.80
3.75
12V SUPPLIES
12V SUPPLIES
9.9958
9.9955
9.9952
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
(V)
SOURCE CURRENT (mA)
SINK CURRENT (mA)
LOGIC
SYNC
Figure 26. Supply Current vs. Logic Input Current for SCLK,
LDAC
, SDIN,
Figure 29. Source and Sink Capability of Output Amplifier
with Full Scale Loaded
and
Increasing and Decreasing
Rev. 0 | Page 14 of 24
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