ADV7390/ADV7391/ADV7392/ADV7393
Table 23. Register 0x80 to Register 0x83
SR7 to
Bit Number
Reset
Value
0x10
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Register Setting
NTSC
PAL B, PAL D, PAL G, PAL H, PAL I
PAL M
0x80
SD Mode
Register 1
SD Standard.
PAL N
SD Luma Filter.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LPF NTSC
LPF PAL
Notch NTSC
Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Reserved
SD Chroma Filter.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.3 MHz
0.65 MHz
1.0 MHz
2.0 MHz
Reserved
Chroma CIF
Chroma QCIF
3.0 MHz
0x82
SD Mode
Register 2
SD PrPb SSAF Filter.
SD DAC Output 1.
0
1
Disabled
Enabled
0x0B
0
1
Refer to Table 32 in the Output
Configuration section
Reserved.
0
SD Pedestal.
0
1
Disabled
Enabled
SD Square Pixel Mode.
SD VCR FF/RW Sync.
SD Pixel Data Valid.
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Disabled
Enabled
SD Active Video Edge
Control.
0
1
Disabled
Enabled
0x83
SD Mode
Register 3
SD Pedestal YPrPb Output.
0
1
No pedestal on YPrPb
7.5 IRE pedestal on YPrPb
Y = 700 mV/300 mV
Y = 714 mV/286 mV
700 mV p-p (PAL), 1000 mV p-p (NTSC)
700 mV p-p
0x04
SD Output Levels Y.
0
1
SD Output Levels PrPb.
0
0
1
1
0
1
0
1
1000 mV p-p
648 mV p-p
SD Vertical Blanking
Interval (VBI) Open.
0
1
Disabled
Enabled
SD Closed Captioning
Field Control.
0
0
1
1
0
1
0
1
Closed captioning disabled
Closed captioning on odd field only
Closed captioning on even field only
Closed captioning on both fields
Reserved
Reserved.
0
Rev. 0 | Page 34 of 96
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