Data Sheet
ADV7180
48-LEAD LQFP
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
DGND
DVDDIO
SFL
A
A
A
A
6
5
4
3
IN
IN
IN
IN
PIN 1
3
4
DVDDIO
GPO1
GPO0
P7
5
AGND
AVDD
ADV7180
6
LQFP
TOP VIEW
(Not to Scale)
7
VFEFN
VREFP
AGND
8
P6
9
P5
10
11
12
P4
A
A
2
1
IN
IN
P3
P2
PVDD
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 11. 48-Lead LQFP Pin Configuration
Table 12. 48-Lead LQFP Pin Function Descriptions
Pin No.
Mnemonic
Type Description
1, 13, 19, 43
2, 4
3
DGND
DVDDIO
SFL
G
P
O
Digital Ground.
Digital I/O Supply Voltage (1.8V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
5, 6, 41, 42
7 to 12, 20, 22
14
GPO0 to GPO3
P7 to P2, P1, P0
LLC
O
O
O
15, 48
16
NC
XTAL1
No Connect Pins. These pins are not connected internally.
O
I
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
17
XTAL
18, 44
21
DVDD
PWRDWN
AGND
P
I
Digital Supply Voltage (1.8 V).
A logic low on this pin places the ADV7180 in power-down mode.
Analog Ground.
23, 28, 32
G
24
25
ELPF
PVDD
AIN1 to AIN6
VREFP
VREFN
AVDD
I
P
I
O
O
P
I
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 57.
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
26, 27, 33 to 36
29
30
31
37
RESET
38
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
39
40
45
46
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
47
HS
O
Horizontal Synchronization Output Signal.
Rev. G | Page 17 of 120
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