ADV7180
Data Sheet
40-LEAD LFCSP
PIN 1
DVDDIO
SFL
DGND
DVDDIO
P7
1
2
3
4
5
6
7
8
9
30
29
A
A
3
2
IN
IN
INDICATOR
28 AGND
27 AVDD
26 VREFN
25 VREFP
24 AGND
23 A 1
22 TEST_0
21 AGND
ADV7180
LFCSP
P6
P5
P4
P3
TOP VIEW
(Not to Scale)
IN
P2 10
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 9. 40-Lead LFCSP Pin Configuration
Table 10. 40-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
DVDDIO
SFL
Type
Description
1, 4
2
P
O
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
3, 15, 35, 40
5 to 10, 16, 17
11
DGND
P7 to P2, P1, P0
LLC
G
O
O
Ground for Digital Supply.
Video Pixel Output Port.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
12
13
XTAL1
XTAL
O
I
This pin should be connected to the 28.6363 MHz crystal or not connected if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
14, 36
18
DVDD
PWRDWN
ELPF
PVDD
AGND
TEST_0
AIN1 to AIN3
VREFP
VREFN
AVDD
P
I
Digital Supply Voltage (1.8 V).
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 55.
PLL Supply Voltage (1.8 V).
Ground for Analog Supply.
This pin must be tied to DGND.
19
20
21, 24, 28
22
I
P
G
I
23, 29, 30
I
Analog Video Input Channels.
25
26
27
31
O
O
P
I
Internal Voltage Reference Output. See Figure 55 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 55 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
RESET
32
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
33
34
37
38
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
39
HS
EPAD (EP)
O
Horizontal Synchronization Output Signal.
The exposed pad must be connected to GND.
Rev. G | Page 14 of 120
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