Data Sheet
ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32-LEAD LFCSP
PIN1
HS 1
DGND 2
DVDDIO 3
SFL 4
INDICATOR
24 A
23 A
3
2
IN
IN
22 AVDD
21 VREFN
20 VREFP
ADV7180
LFCSP
P7 5
P6 6
P5 7
TOP VIEW
(Not to Scale)
19 A
1
IN
18 PVDD
17 ELPF
P4 8
NOTES
1. THE EXPOSEDPAD MUST BE CONNECTEDTO GND.
Figure 8. 32-Lead LFCSP Pin Configuration
Table 9. 32-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
2, 29
3
4
HS
O
G
P
O
Horizontal Synchronization Output Signal.
Ground for Digital Supply.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
DGND
DVDDIO
SFL
5 to 10, 15, 16
11
P7 to P2, P1, P0
LLC
O
O
Video Pixel Output Port.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
12
13
XTAL1
XTAL
O
I
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V,28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
14, 30
17
18
19, 23, 24
20
21
DVDD
ELPF
PVDD
AIN1 to AIN3
VREFP
VREFN
AVDD
P
I
P
I
O
O
P
I
Digital Supply Voltage (1.8 V).
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 58.
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
22
25
RESET
26
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
27
28
31
32
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
EPAD (EP)
The exposed pad must be connected to GND.
Rev. G | Page 13 of 120