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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
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Data Sheet  
ADV7180  
INPUT CONFIGURATION  
Table 13. 64-Lead and 48-Lead LQFP INSEL[3:0]  
The following are the two key steps for configuring the  
ADV7180 to correctly decode the input video:  
INSEL[3:0]  
Video Format  
Composite  
Composite  
Composite  
Composite  
Composite  
Composite  
Y/C (S-Video)  
Analog Input  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
CVBS input on AIN1  
CVBS input on AIN2  
CVBS input on AIN3  
CVBS input on AIN4  
CVBS input on AIN5  
CVBS input on AIN6  
Y input on AIN1  
C input on AIN4  
Y input on AIN2  
C input on AIN5  
Y input on AIN3  
C input on AIN6  
Y input on AIN1  
Pb input on AIN4  
Pr input on AIN5  
Y input on AIN2  
Pr input on AIN6  
Pb input on AIN3  
Reserved  
1. Use INSEL[3:0] to configure the routing and format decoding  
(CVBS, Y/C, or YPrPb). For the 64-lead and 48-lead L QF P,  
see Table 13. For the 40-lead and 32-lead LFCSP, see Table 14.  
2. If the input requirements are not met using the INSEL[3:0]  
options, the analog input muxing section must be configured  
manually to correctly route the video from the analog  
input pins to the ADC. The standard definition processor  
block, which decodes the digital data, should be configured  
to process the CVBS, Y/C, or YPrPb format. This is performed  
by INSEL[3:0] selection.  
0111  
1000  
1001  
Y/C (S-Video)  
Y/C (S-Video)  
YPrPb  
CONNECT ANALOG VIDEO  
SIGNALS TO ADV7180.  
SET INSEL[3:0] TO CONFIGURE  
VIDEO FORMAT. USE PREDEFINED  
FORMAT/ROUTING.  
1010  
YPrPb  
NO  
1011 to 1111  
Reserved  
YES  
LQFP-64  
LQFP-48  
LFCSP-40  
LFCSP-32  
Table 14. 40-Lead and 32-Lead LFCSP INSEL[3:0]  
CONFIGURE ADC INPUTS USING  
MANUAL MUXING CONTROL BITS:  
MUX_0[2:0], MUX_1[2:0], MUX_2[2:0].  
SEE TABLE 15.  
INSEL[3:0]  
Video Format  
Composite  
Reserved  
Composite  
Composite  
Reserved  
Analog Input  
CVBS input on AIN1  
Reserved  
CVBS input on AIN2  
CVBS input on AIN3  
Reserved  
REFER TO  
TABLE 13  
REFER TO  
TABLE 14  
0000  
0001 to 0010  
0011  
0100  
0101  
Figure 14. Signal Routing Options  
INSEL[3:0], Input Selection, Address 0x00[3:0]  
The INSEL bits allow the user to select the input format. They  
also configure the standard definition processor core to process  
composite (CVBS), S-Video (Y/C), or component (YPrPb) format.  
0110  
Y/C (S-Video)  
Y input on AIN1  
C input on AIN2  
Reserved  
Y input on AIN1  
Pr input on AIN3  
Pb input on AIN2  
Reserved  
0111 to 1000  
1001  
Reserved  
YPrPb  
INSEL[3:0] has predefined analog input routing schemes that  
do not require manual mux programming (see Table 13 and  
Table 14). This allows the user to route the various video signal  
types to the decoder and select them using INSEL[3:0] only.  
The added benefit is that if, for example, the CVBS input is  
selected, the remaining channels are powered down.  
1010 to 1111  
Reserved  
Rev. G | Page 19 of 120  
 
 
 
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