Data Sheet
ADV7180
64-LEAD LQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INTRQ
HS
A
A
A
5
4
3
IN
IN
IN
PIN 1
3
DGND
DVDDIO
P11
4
NC
NC
5
6
P10
AGND
NC
ADV7180
7
P9
LQFP
TOP VIEW
(Not to Scale)
8
P8
NC
9
SFL
AVDD
VREFN
VREFP
AGND
10
11
12
13
14
15
16
DGND
DVDDIO
GPO1
GPO0
P7
A
A
2
1
IN
IN
P6
TEST_0
NC
P5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 10. 64-Lead LQFP Pin Configuration
Table 11. 64-Lead LQFP Pin Function Description
Pin No.
Mnemonic
Type Description
1
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 108).
2
HS
DGND
DVDDIO
O
G
P
Horizontal Synchronization Output Signal.
Digital Ground.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
3, 10, 24, 57
4, 11
5 to 8, 14 to 19,
25, 26, 59 to 62
P11 to P8,
P7 to P2, P1,
P0, P15 to P12
O
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
9
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
12, 13, 55, 56
20
GPO0 to GPO3
LLC
O
O
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
21
XTAL1
XTAL
O
I
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode,
the crystal must be a fundamental crystal.
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external
1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental
crystal.
22
23, 58
DVDD
P
Digital Supply Voltage (1.8 V).
27, 28, 33, 41, 42, NC
44, 45, 50
No Connect. These pins are not connected internally.
29
PWRDWN
I
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 56.
PLL Supply Voltage (1.8 V).
Analog Ground.
This pin must be tied to DGND.
30
31
ELPF
PVDD
AGND
TEST_0
AIN1 to AIN6
I
P
G
I
32, 37, 43
34
35, 36, 46 to 49
I
Analog Video Input Channels.
Rev. G | Page 15 of 120
ADI [ ADI ]
