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ADV7171KSUZ-REEL 参数 Datasheet PDF下载

ADV7171KSUZ-REEL图片预览
型号: ADV7171KSUZ-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: 数字PAL / NTSC视频编码器 [Digital PAL/NTSC Video Encoder]
分类和应用: 转换器色度信号转换器消费电路商用集成电路编码器
文件页数/大小: 64 页 / 865 K
品牌: ADI [ ADI ]
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ADV7170/ADV7171  
REGISTER PROGRAMMING  
This section describes each register, including subaddress  
register, mode registers, subcarrier frequency registers,  
subcarrier phase register, timing registers, closed captioning  
extended data registers, closed captioning data registers, and  
NTSC pedestal control registers, in terms of its configuration.  
MODE REGISTER 0 MR0 (MR07 TO MR00)  
(Address [SR4 to SR0] = 00H)  
Figure 38 shows the various operations under the control of  
Mode Register 0. This register can be read from as well as  
written to.  
SUBADDRESS REGISTER (SR7 TO SR0)  
MR0 BIT DESCRIPTION  
Output Video Standard Selection (MR01 to MR00)  
The communications register is an 8-bit, write-only register.  
After the part has been accessed over the bus and a read/write  
operation is selected, the subaddress is set up. The subaddress  
register determines to/from which register the operation takes  
place.  
These bits are used to set up the encode mode. The ADV7170/  
ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and  
PAL M/N standard video.  
Luminance Filter Control (MR02 to MR04)  
Figure 37 shows the various operations under the control of the  
subaddress register. Zero should always be written to SR7 to SR6.  
These bits specify which luma filter is to be selected. The filter  
selection is made independent of whether PAL or NTSC is  
selected.  
REGISTER SELECT (SR5 TO SR0)  
These bits are set up to point to the required starting address.  
Chrominance Filter Control (MR05 to MR07)  
These bits select the chrominance filter. A low-pass filter can be  
selected with a choice of cutoff frequencies, 0.65 MHz,  
1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF  
or QCIF filters.  
WRITE  
S
S
SLAVE ADDR A(S)  
LSB = 0  
SUBADDR  
SUBADDR  
A(S)  
A(S)  
DATA  
A(S)  
DATA  
A(S) P  
SEQUENCE  
LSB = 1  
READ  
SEQUENCE  
SLAVE ADDR A(S)  
S
SLAVE ADDR A(S)  
DATA  
A(M)  
DATA  
A(M) P  
S = START BIT  
P = STOP BIT  
A(S) = ACKNOWLEDGE BY SLAVE  
A(M) = ACKNOWLEDGE BY MASTER  
A (S) = NO-ACKNOWLEDGE BY SLAVE  
A (M) = NO-ACKNOWLEDGE BY MASTER  
Figure 36. Write and Read Sequences  
Rev. C | Page 28 of 64  
 
 
 
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