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ADV7123KSTZ140 参数 Datasheet PDF下载

ADV7123KSTZ140图片预览
型号: ADV7123KSTZ140
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz的三路10位高速视频DAC [CMOS, 330 MHz Triple 10-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器PC
文件页数/大小: 24 页 / 340 K
品牌: AD [ ANALOG DEVICES ]
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ADV7123
Parameter
Total Harmonic Distortion
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
T
A
= 25°C
T
MIN
to T
MAX
f
CLK
= 50 MHz; f
OUT
= 2.00 MHz
f
CLK
= 100 MHz; f
OUT
= 2.00 MHz
f
CLK
= 140 MHz; f
OUT
= 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk
Data Feedthrough
Clock Feedthrough
1
2
Min
Typ
Max
Unit
66
65
64
64
55
10
23
22
33
dBc
dBc
dBc
dBc
dBc
pV-sec
dB
dB
dB
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
REF
.
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
5 V TIMING SPECIFICATIONS
V
AA
= 5 V ± 5%,
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
unless otherwise noted, T
J MAX
= 110°C.
Table 5.
Parameter
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
Analog Output Skew
CLOCK CONTROL
CLOCK Frequency
Symbol
t
6
t
7
t
8
t
9
f
CLK
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Min
Typ
5.5
1.0
15
1
Max
Unit
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
50 MHz grade
140 MHz grade
240 MHz grade
Conditions
2
50
140
240
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay
PSAVE Up Time
1
2
t
1
t
2
t
3
t
4
t
5
t
4
t
5
t
4
t
5
t
PD
t
10
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
1.0
2
1.0
10
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Rev. D | Page 7 of 24