欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADV7123KSTZ140 参数 Datasheet PDF下载

ADV7123KSTZ140图片预览
型号: ADV7123KSTZ140
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz的三路10位高速视频DAC [CMOS, 330 MHz Triple 10-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器PC
文件页数/大小: 24 页 / 340 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号ADV7123KSTZ140的Datasheet PDF文件第4页浏览型号ADV7123KSTZ140的Datasheet PDF文件第5页浏览型号ADV7123KSTZ140的Datasheet PDF文件第6页浏览型号ADV7123KSTZ140的Datasheet PDF文件第7页浏览型号ADV7123KSTZ140的Datasheet PDF文件第9页浏览型号ADV7123KSTZ140的Datasheet PDF文件第10页浏览型号ADV7123KSTZ140的Datasheet PDF文件第11页浏览型号ADV7123KSTZ140的Datasheet PDF文件第12页  
ADV7123
3.3 V TIMING SPECIFICATIONS
V
AA
= 3.0 V to 3.6 V,
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
unless otherwise noted, T
J MAX
= 110°C.
Table 6.
Parameter
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
Analog Output Skew
CLOCK CONTROL
CLOCK Frequency
Symbol
t
6
t
7
t
8
t
9
f
CLK
Min
Typ
7.5
1.0
15
12
50
140
240
330
0.2
1.5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Max
Unit
ns
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
50 MHz grade
140 MHz grade
240 MHz grade
330 MHz grade
Conditions
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay
PSAVE Up Time
1
2
t
1
t
2
t
3
t
4
t
5
t
4
t
5
t
4
t
5
t
4
t
5
t
PD
t
10
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
1.0
4
1.0
10
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
t
3
t
4
t
5
CLOCK
t
2
DIGITAL INPUTS
(R9 TO R0, G9 TO G0, B9 TO B0,
SYNC, BLANK)
t
1
t
6
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t
8
t
7
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
Figure 2. Timing Diagram
Rev. D | Page 8 of 24
00215-002