ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
EEPROM
64k × 16-BIT
ADuC7026/
ADuC7027
Table 198. XMxPAR Registers
A16
Name
Address
Default Value
Access
R/W
AD15:AD0
D0:D15
A0:A15
XM0PAR
XM1PAR
XM2PAR
XM3PAR
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
0x70FF
0x70FF
0x70FF
0x70FF
R/W
LATCH
R/W
AE
R/W
MS0
MS1
CS
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
WS
RS
WE
OE
Table 199. XMxPAR MMR Bit Descriptions
RAM
128k × 8-BIT
Bit
Description
D0:D7
15
Enable byte write strobe. This bit is used only for two,
8-bit memory devices sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE and BLE signals. Cleared by user to use BHE and BLE
signals.
A16
A0:A15
CS
WE
OE
Figure 82. Interfacing to External EEPROM/RAM
14:12 Number of wait states on the address latch enable STROBE.
11
10
Reserved.
Table 195. XMCFG Register
Extra address hold time. Set by user to disable extra hold
time. Cleared by user to enable one clock cycle of hold
on the address in read and write.
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
9
Extra bus transition time on read. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the read strobe (RS).
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
8
Extra bus transition time on write. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the write strobe (WS).
Table 196. XMxCON Registers
7:4
3:0
Number of write wait states. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Number of read wait states. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Name
Address
Default Value
0x00
Access
R/W
XM0CON
XM1CON
XM2CON
XM3CON
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
0x00
R/W
0x00
R/W
0x00
R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Figure 83, Figure 84, Figure 85, and Figure 86 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
Table 197. XMxCON MMR Bit Descriptions
Bit Description
1
Selects data bus width. Set by user to select a 16-bit data
bus. Cleared by user to select an 8-bit data bus.
0
Enables memory region. Set by user to enable the memory
region. Cleared by user to disable the memory region.
Rev. F | Page 90 of 104
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