ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Both switching edges are moved by an equal amount
(PWMDAT1 × tCORE) to preserve the symmetrical output
patterns.
In general, the on times of the PWM signals in double update
mode can be defined as follows:
On the high side
Also shown are the PWMSYNC pulse and Bit 0 of the
PWMSTA register, which indicates whether operation is in the
first or second half cycle of the PWM period.
t0HH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
t
0HL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
The resulting on times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
where Subscript 1 refers to the value of that register during the
first half cycle, and Subscript 2 refers to the value during the
second half cycle.
On the high side
t
t
0HH = PWMDAT0 + 2(PWMCH0 − PWMDAT1) × tCORE
0HL = PWMDAT0 − 2(PWMCH0 − PWMDAT1) × tCORE
The corresponding duty cycles (d) are
d0H = t0HH/tS = (PWMDAT01/2 + PWMDAT02/2 +
and the corresponding duty cycles (d)
0H = t0HH/tS = ½ + (PWMCH0 − PWMDAT1)/PWMDAT0
and on the low side
PWMCH01 + PWMCH02 − PWMDAT11 − PWMDAT12)/
(PWMDAT01 + PWMDAT02)
d
On the low side
t0LH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
t
t
0LH = PWMDAT0 − 2(PWMCH0 + PWMDAT1) × tCORE
0LL = PWMDAT0 + 2(PWMCH0 + PWMDAT1) × tCORE
t
0LL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
and the corresponding duty cycles (d)
OL = t0LH/tS = ½ − (PWMCH0 + PWMDAT1)/PWMDAT0
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
d
where Subscript 1 refers to the value of that register during the
first half cycle, and Subscript 2 refers to the value during the
second half cycle.
The minimum permissible t0H and t0L values are zero,
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is tS, corresponding to a 100% duty cycle.
The corresponding duty cycles (d) are
Figure 70 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. The same value
for any or all of these quantities can be used in both halves of the
PWM cycle. However, there is no guarantee that symmetrical
PWM signals are produced by the timing unit in double update
mode. Figure 70 also shows that the dead time insertions into
the PWM signals are done in the same way as in single update
mode.
d0L = t0LH/tS = (PWMDAT01/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 + PWMDAT11 +
PWMDAT12)/(PWMDAT01 + PWMDAT02)
For the completely general case in double update mode
(see Figure 70), the switching period is given by
tS = (PWMDAT01 + PWMDAT02) × tCORE
Again, the values of t0H and t0L are constrained to lie between
zero and tS.
PWM signals similar to those illustrated in Figure 69 and
Figure 70 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. When these registers are written, internal
counting of the timers in the 3-phase timing unit is enabled.
–PWMDAT0 ÷ 2
2
+PWMDAT0 ÷ 2
2
–PWMDAT0 ÷ 2
1
0
+PWMDAT0 ÷ 2
1
0
PWMCH0
PWMCH0
2
1
0H
2 × PWMDAT1
2
2 × PWMDAT1
1
0L
Writing to the PWMDAT0 register starts the internal timing of
the main PWM timer. Provided that the PWMDAT0 register is
written to prior to the PWMCH0, PWMCH1, and PWMCH2
registers in the initialization, the first PWMSYNC pulse and
interrupt (if enabled) appear 1.5 × tCORE × PWMDAT0 seconds
after the initial write to the PWMDAT0 register in single update
mode. In double update mode, the first PWMSYNC pulse
appears after PWMDAT0 × tCORE seconds.
PWMSYNC
PWMDAT2 + 1
PWMDAT2 + 1
2
1
PWMSTA (0)
PWMDAT0
PWMDAT0
2
1
Figure 70. Typical PWM Outputs of the 3-Phase Timing Unit
(Double Update Mode)
Rev. F | Page 64 of 104
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