ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Therefore, for a 41.78 MHz fCORE, the fundamental time increment
is 24 ns. The value written to the PWMDAT0 register is effectively
the number of fCORE clock increments in one-half a PWM
period. The required PWMDAT0 value is a function of the
desired PWM switching frequency (fPWN) and is given by
DESCRIPTION OF THE PWM BLOCK
A functional block diagram of the PWM controller is shown in
Figure 68. The generation of the six output PWM signals on
Pin PWM0H to Pin PWM2L is controlled by the following four
important blocks:
PWMDAT0 = fCORE/(2 × fPWM
)
•
•
The 3-phase PWM timing unit. The core of the PWM
controller, this block generates three pairs of complemented
and dead-time-adjusted, center-based PWM signals. This
unit also generates the internal synchronization pulse,
PWMSYNC. It also controls whether the external PWMSYNC
pin is used.
The output control unit. This block can redirect the
outputs of the 3-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling
of each of the six PWM output signals.
The gate drive unit. This block can generate the high
frequency chopping and its subsequent mixing with the
PWM signals.
The PWM shutdown controller. This block controls the
PWM shutdown via the PWMTRIP pin and generates the
correct reset signal for the timing unit.
Therefore, the PWM switching period, tS, can be written as
tS = 2 × PWMDAT0 × tCORE
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of
f
PWM(min) = 41.78 × 106/(2 × 65,535) = 318.75 Hz
Note that PWMDAT0 values of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
•
•
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The PWM controller is driven by the ADuC7019/20/21/22/24/
25/26/27/28/29 core clock frequency and is capable of generating
two interrupts to the ARM core. One interrupt is generated on
the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the dead
time inserted into all three pairs of PWM output signals. The dead
time, tD, is related to the value in the PWMDAT1 register by
3-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit
of the PWM controller is
tD = PWMDAT1 × 2 × tCORE
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can, therefore, be programmed in
increments of 2tCORE (or 49 ns for a 41.78 MHz core clock).
tCORE = 1/fCORE
where fCORE is the core frequency of the MicroConverter.
CONFIGURATION
REGISTERS
DUTY CYCLE
REGISTERS
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
PWMCH0
PWMCH1
PWMCH2
PWMEN
PWMCFG
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
3-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
PWM
SHUTDOWN
CONTROLLER
CORE CLOCK
SYNC
PWM
PWM
SYNC
TO INTERRUPT
CONTROLLER
TRIP
Figure 68. Overview of the PWM Controller
Rev. F | Page 62 of 104
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