ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
MMRs and Keys
Table 63. POWCON Register
Name
Address
Default Value
0x0003
Access
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs: PLLCON (see Table 61)
and POWCON (see Table 64). PLLCON controls the operating
mode of the clock system, whereas POWCON controls the core
clock frequency and the power-down mode.
POWCON
0xFFFF0408
R/W
Table 64. POWCON MMR Bit Designations
Bit Name Value
7
Description
Reserved.
To prevent accidental programming, a certain sequence (see
Table 65) must be followed to write to the PLLCON and
POWCON registers.
6:4 PC
000
Operating modes.
Active mode.
Pause mode.
Nap.
Sleep mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
001
010
011
Table 59. PLLKEYx Registers
Name
Address
Default Value
0x0000
Access
W
PLLKEY1
PLLKEY2
0xFFFF0410
0xFFFF0418
100
Stop mode. IRQ0 to IRQ3 can wake up
the part.
0x0000
W
Others
Reserved.
Reserved.
Table 60. PLLCON Register
3
Name
Address
Default Value
Access
2:0 CD
000
001
010
011
100
101
110
111
CPU clock divider bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
PLLCON
0xFFFF0414
0x21
R/W
Table 61. PLLCON MMR Bit Designations
Bit
7:6
5
Name
Value Description
Reserved.
32 kHz PLL input selection. Set by
user to select the internal 32 kHz
oscillator. Set by default. Cleared by
user to select the external 32 kHz crystal.
OSEL
4:2
1:0
Reserved.
Clocking modes.
Reserved.
PLL. Default configuration.
Reserved.
External clock on the P0.7 pin.
Table 65. PLLCON and POWCON Write Sequence
MDCLK
PLLCON
POWCON
00
01
10
11
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
POWKEY1 = 0x01
POWCON = user value
POWKEY2 = 0xF4
Table 62. POWKEYx Registers
Name
Address
Default Value
0x0000
Access
W
POWKEY1
POWKEY2
0xFFFF0404
0xFFFF040C
0x0000
W
Rev. F | Page 60 of 104
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