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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
OTHER ANALOG PERIPHERALS  
DAC  
Table 51. DACxDAT Registers  
Name  
Address  
Default Value  
Access  
R/W  
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two,  
three, or four 12-bit voltage output DACs on-chip, depending on  
the model. Each DAC has a rail-to-rail voltage output buffer  
capable of driving 5 kΩ/100 pF.  
DAC0DAT  
DAC1DAT  
DAC2DAT  
DAC3DAT  
0xFFFF0604  
0xFFFF060C  
0xFFFF0614  
0xFFFF061C  
0x00000000  
0x00000000  
0x00000000  
0x00000000  
R/W  
R/W  
R/W  
Each DAC has three selectable ranges: 0 V to VREF (internal  
band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD.  
DACREF is equivalent to an external reference for the DAC.  
The signal range is 0 V to AVDD.  
Table 52. DAC0DAT MMR Bit Designations  
Bit  
Description  
31:28  
27:16  
15:0  
Reserved.  
12-bit data for DAC0.  
Reserved.  
MMRs Interface  
Each DAC is independently configurable through a control  
register and a data register. These two registers are identical for  
the four DACs. Only DAC0CON (see Table 50) and DAC0DAT  
(see Table 52) are described in detail in this section.  
Using the DACs  
The on-chip DAC architecture consists of a resistor string DAC  
followed by an output buffer amplifier. The functional equivalent  
is shown in Figure 63.  
Table 49. DACxCON Registers  
Name  
Address  
Default Value  
0x00  
Access  
R/W  
AV  
DD  
REF  
REF  
DAC0CON  
DAC1CON  
DAC2CON  
DAC3CON  
0xFFFF0600  
0xFFFF0608  
0xFFFF0610  
0xFFFF0618  
V
DAC  
0x00  
R/W  
R
R
R
0x00  
R/W  
0x00  
R/W  
DAC0  
Table 50. DAC0CON MMR Bit Designations  
Bit Name  
Value  
Description  
7:6  
Reserved.  
5
DACCLK  
DACCLR  
DAC update rate. Set by user to  
update the DAC using Timer1.  
Cleared by user to update the DAC  
using HCLK (core clock).  
DAC clear bit. Set by user to enable  
normal DAC operation. Cleared by  
user to reset data register of the DAC  
to 0.  
Reserved. This bit should be left at 0.  
Reserved. This bit should be left at 0.  
DAC range bits.  
Power-down mode. The DAC output is  
in three-state.  
R
R
4
Figure 63. DAC Structure  
As illustrated in Figure 63, the reference source for each DAC is  
user-selectable in software. It can be AVDD, VREF, or DACREF. In  
0-to-AVDD mode, the DAC output transfer function spans from  
0 V to the voltage at the AVDD pin. In 0-to-DACREF mode, the  
DAC output transfer function spans from 0 V to the voltage at the  
DACREF pin. In 0-to-VREF mode, the DAC output transfer function  
3
2
1:0  
00  
01  
10  
11  
0 V to DACREF range.  
0 V to VREF (2.5 V) range.  
0 V to AVDD range.  
spans from 0 V to the internal 2.5 V reference, VREF  
.
The DAC output buffer amplifier features a true, rail-to-rail  
output stage implementation. This means that when unloaded,  
each output is capable of swinging to within less than 5 mV of  
both AVDD and ground. Moreover, the DAC’s linearity specification  
(when driving a 5 kꢀ resistive load to ground) is guaranteed  
through the full transfer function, except Code 0 to Code 100,  
and, in 0-to-AVDD mode only, Code 3995 to Code 4095.  
Rev. F | Page 56 of 104