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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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Data Sheet  
ADuC7019/20/21/22/24/25/26/27/28/29  
Linearity degradation near ground and AVDD is caused by satu-  
ration of the output amplifier, and a general representation of its  
effects (neglecting offset and gain error) is illustrated in Figure 64.  
The dotted line in Figure 64 indicates the ideal transfer function,  
and the solid line represents what the transfer function may  
look like with endpoint nonlinearities due to saturation of the  
output amplifier. Note that Figure 64 represents a transfer function  
in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF mode  
(with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is  
similar. However, the upper portion of the transfer function  
follows the ideal line right to the end (VREF in this case, not AVDD),  
showing no signs of endpoint linearity errors.  
Table 54. PSMCON MMR Bit Descriptions  
Bit Name  
Description  
3
CMP  
Comparator bit. This is a read-only bit that  
directly reflects the state of the comparator.  
Read 1 indicates that the IOVDD supply is above  
its selected trip point or that the PSM is in  
power-down mode. Read 0 indicates that the  
IOVDD supply is below its selected trip point. This  
bit should be set before leaving the interrupt  
service routine.  
2
1
TP  
Trip point selection bit. 0 = 2.79 V, 1 = 3.07 V.  
PSMEN Power supply monitor enable bit. Set to 1 to  
enable the power supply monitor circuit. Cleared  
to 0 to disable the power supply monitor circuit.  
AV  
DD  
0
PSMI  
Power supply monitor interrupt bit. This bit is set  
high by the MicroConverter after CMP goes low,  
indicating low I/O supply. The PSMI bit can be  
used to interrupt the processor. After CMP  
returns high, the PSMI bit can be cleared by  
writing a 1 to this location. A 0 write has no  
effect. There is no timeout delay; PSMI can be  
immediately cleared after CMP goes high.  
AV – 100mV  
DD  
COMPARATOR  
100mV  
The ADuC7019/20/21/22/24/25/26/27/28/29 integrate voltage  
comparators. The positive input is multiplexed with ADC2, and  
the negative input has two options: ADC3 and DAC0. The output  
of the comparator can be configured to generate a system inter-  
rupt, be routed directly to the programmable logic array, start  
an ADC conversion, or be on an external pin, CMPOUT, as  
shown in Figure 65.  
0x00000000  
0x0FFF0000  
Figure 64. Endpoint Nonlinearities Due to Amplifier Saturation  
The endpoint nonlinearities conceptually illustrated in  
Figure 64 get worse as a function of output loading. Most  
of the ADuC7019/20/21/22/24/25/26/27/28/29 data sheet  
specifications assume a 5 kΩ resistive load to ground at the  
DAC output. As the output is forced to source or sink more  
current, the nonlinear regions at the top or bottom (respectively)  
of Figure 64 become larger. With larger current demands, this  
can significantly limit output voltage swing.  
IRQ  
ADC2/CMP0  
MUX  
ADC3/CMP1  
MUX  
DAC0  
POWER SUPPLY MONITOR  
P0.0/CMP  
OUT  
The power supply monitor regulates the IOVDD supply on the  
ADuC7019/20/21/22/24/25/26/27/28/29. It indicates when the  
IOVDD supply pin drops below one of two supply trip points.  
The monitor function is controlled via the PSMCON register.  
If enabled in the IRQEN or FIQEN register, the monitor  
interrupts the core using the PSMI bit in the PSMCON MMR.  
This bit is immediately cleared after CMP goes high.  
Figure 65. Comparator  
Note that because the ADuC7022, ADuC7025, and ADu7027  
parts do not support a DAC0 output, it is not possible to use  
DAC0 as a comparator input on these parts.  
Hysteresis  
This monitor function allows the user to save working registers  
to avoid possible data loss due to low supply or brown-out  
conditions. It also ensures that normal code execution does  
not resume until a safe supply level is established.  
Figure 66 shows how the input offset voltage and hysteresis  
terms are defined.  
CMP  
OUT  
V
V
H
H
Table 53. PSMCON Register  
Name  
Address  
Default Value  
Access  
PSMCON  
0xFFFF0440  
0x0008  
R/W  
CMP0  
V
OS  
Figure 66. Comparator Hysteresis Transfer Function  
Rev. F | Page 57 of 104