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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
Input offset voltage (VOS) is the difference between the center of  
the hysteresis range and the ground level. This can either be  
positive or negative. The hysteresis voltage (VH) is one-half the  
width of the hysteresis range.  
OSCILLATOR AND PLL—POWER CONTROL  
Clocking System  
Each ADuC7019/20/21/22/24/25/26/27/28/29 integrates a  
32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL  
locks onto a multiple (1275) of the internal oscillator or an external  
32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for  
the system. To allow power saving, the core can operate at this  
frequency, or at binary submultiples of it. The actual core oper-  
ating frequency, UCLK/2CD, is refered to as HCLK. The default  
core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz.  
The core clock frequency can also come from an external clock  
on the ECLK pin as described in Figure 67. The core clock can  
be outputted on ECLK when using an internal oscillator or  
external crystal.  
Comparator Interface  
The comparator interface consists of a 16-bit MMR, CMPCON,  
which is described in Table 56.  
Table 55. CMPCON Register  
Name  
Address  
Default Value  
Access  
CMPCON  
0xFFFF0444  
0x0000  
R/W  
Table 56. CMPCON MMR Bit Descriptions  
Bit  
Name  
Value Description  
15:11  
10  
Reserved.  
Note that when the ECLK pin is used to output the core clock,  
the output signal is not buffered and is not suitable for use as a  
clock source to an external device without an external buffer.  
CMPEN  
Comparator enable bit. Set by user  
to enable the comparator. Cleared  
by user to disable the comparator.  
9:8  
7:6  
5
CMPIN  
CMPOC  
CMPOL  
Comparator negative input  
select bits.  
AVDD/2.  
ADC3 input.  
DAC0 output.  
Reserved.  
Comparator output configuration  
bits.  
XCLKO  
XCLKI  
WATCHDOG  
TIMER  
INT. 32kHz*  
OSCILLATOR  
CRYSTAL  
OSCILLATOR  
00  
01  
10  
11  
OCLK  
WAKE-UP  
TIMER  
AT POWER-UP  
32.768kHz  
41.78MHz  
00  
01  
10  
11  
Reserved.  
Reserved.  
PLL  
P0.7/XCLK  
MDCLK  
Output on CMPOUT  
IRQ.  
.
UCLK  
ANALOG  
PERIPHERALS  
2
I C  
Comparator output logic state bit.  
When low, the comparator output  
is high if the positive input (CMP0)  
is above the negative input (CMP1).  
When high, the comparator output  
is high if the positive input is below  
the negative input.  
CD  
/2  
CD  
CORE  
HCLK  
*32.768kHz ±3%  
P0.7/ECLK  
Figure 67. Clocking System  
4:3  
CMPRES  
Response time.  
The selection of the clock source is in the PLLCON register. By  
default, the part uses the internal oscillator feeding the PLL.  
00  
11  
5 µs response time is typical for  
large signals (2.5 V differential).  
17 µs response time is typical for  
small signals (0.65 mV differential).  
External Crystal Selection  
To switch to an external crystal, the user must do the following:  
3 µs typical.  
1. Enable the Timer2 interrupt and configure it for a timeout  
period of >120 µs.  
2. Follow the write sequence to the PLLCON register, setting  
the MDCLK bits to 01 and clearing the OSEL bit.  
3. Force the part into NAP mode by following the correct  
write sequence to the POWCON register.  
01/10 Reserved.  
Comparator hysteresis bit. Set by  
2
1
CMPHYST  
CMPORI  
user to have a hysteresis of about  
7.5 mV. Cleared by user to have no  
hysteresis.  
Comparator output rising edge  
interrupt. Set automatically when a  
rising edge occurs on the moni-  
tored voltage (CMP0). Cleared by  
user by writing a 1 to this bit.  
When the part is interrupted from NAP mode by the  
Timer2 interrupt source, the clock source has switched to  
the external clock.  
0
CMPOFI  
Comparator output falling edge  
interrupt. Set automatically when a  
falling edge occurs on the monitored  
voltage (CMP0). Cleared by user.  
Rev. F | Page 58 of 104