ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
RESET AND REMAP
EXECUTION TIME FROM SRAM AND FLASH/EE
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 62.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle; the
access time of the SRAM is 2 ns, and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE): one
cycle to execute the instruction, and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
0xFFFFFFFF
KERNEL
0x0008FFFF
0x00011FFF
FLASH/EE
INTERRUPT
SERVICE ROUTINES
0x00080000
0x00010000
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when the CD Bit = 0).
Also, some dead times are needed before accessing data for any
value of the CD bit.
SRAM
INTERRUPT
SERVICE ROUTINES
MIRROR SPACE
0x00000020
ARM EXCEPTION
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
VECTOR ADDRESSES 0x00000000 0x00000000
Figure 62. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from
SRAM instead of from Flash/EE. This means exceptions are
executed twice as fast, being executed in 32-bit ARM mode with
32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline. A data-processing
instruction involving only the core register does not require any
extra clock cycles. However, if it involves data in Flash/EE, an
extra clock cycle is needed to decode the address of the data,
and two cycles are needed to get the 32-bit data from Flash/EE.
An extra cycle must also be added before fetching another
instruction. Data transfer instructions are more complex and
are summarized in Table 43.
Remap Operation
When a reset occurs on the ADuC7019/20/21/22/24/25/26/27/
28/29, execution automatically starts in the factory-programmed,
internal configuration code. This kernel is hidden and cannot
be accessed by user code. If the part is in normal mode (the BM
pin is high), it executes the power-on configuration routine of
the kernel and then jumps to the reset vector address,
Table 43. Execution Cycles in ARM/Thumb Mode
Fetch
Instructions Cycles
0x00000000, to execute the user’s reset exception routine.
Dead
Time
Dead
Time
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
Data Access
LD1
LDH
LDM/PUSH
STR1
STRH
2/1
2/1
2/1
2/1
2/1
2/1
1
1
N2
1
1
N1
2
1
1
1
N1
1
1
N1
2 × N2
2 × 20 ns
20 ns
The remap is done from Flash/EE by setting Bit 0 of the REMAP
register. Caution must be taken to execute this command from
Flash/EE, above Address 0x00080020, and not from the bottom
of the array because this is replaced by the SRAM.
STRM/POP
2 × N × 20 ns1
1 The SWAP instruction combines an LD and STR instruction with only one
fetch, giving a total of eight cycles + 40 ns.
This operation is reversible. The Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Caution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
2 N is the amount of data to load or store in the multiple load/store instruction
(1 < N ≤ 16).
Rev. F | Page 54 of 104
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