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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
SECURITY  
FLASH/EE CONTROL INTERFACE  
The 62 kB of Flash/EE memory available to the user can be read  
and write protected.  
Serial and JTAG programming use the Flash/EE control interface,  
which includes the eight MMRs outlined in this section.  
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 42) protects  
the 62 kB from being read through JTAG programming mode.  
The other 31 bits of this register protect writing to the flash  
memory. Each bit protects four pages, that is, 2 kB. Write  
protection is activated for all types of access.  
Table 31. FEESTA Register  
Name  
Address  
Default Value  
Access  
FEESTA  
0xFFFFF800  
0x20  
R
FEESTA is a read-only register that reflects the status of the  
flash control interface as described in Table 32.  
Three Levels of Protection  
Table 32. FEESTA MMR Bit Designations  
Protection can be set and removed by writing directly into  
FEEHIDE MMR. This protection does not remain after reset.  
Protection can be set by writing into the FEEPRO MMR. It  
takes effect only after a save protection command (0x0C)  
and a reset. The FEEPRO MMR is protected by a key to  
avoid direct access. The key is saved once and must be  
entered again to modify FEEPRO. A mass erase sets the  
key back to 0xFFFF but also erases all the user code.  
Flash can be permanently protected by using the FEEPRO  
MMR and a particular value of key: 0xDEADDEAD.  
Entering the key again to modify the FEEPRO register  
is not allowed.  
Bit  
15:6  
5
Description  
Reserved.  
Reserved.  
Reserved.  
4
3
Flash interrupt status bit. Set automatically when an  
interrupt occurs, that is, when a command is complete  
and the Flash/EE interrupt enable bit in the FEEMOD  
register is set. Cleared when reading the FEESTA register.  
2
1
0
Flash/EE controller busy. Set automatically when the  
controller is busy. Cleared automatically when the  
controller is not busy.  
Command fail. Set automatically when a command  
completes unsuccessfully. Cleared automatically when  
reading the FEESTA register.  
Command pass. Set by the MicroConverter when a  
command completes successfully. Cleared automatic-  
ally when reading the FEESTA register.  
Sequence to Write the Key  
1. Write the bit in FEEPRO corresponding to the page to be  
protected.  
2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5  
must equal 0).  
Table 33. FEEMOD Register  
3. Write a 32-bit key in FEEADR and FEEDAT.  
4. Run the write key command 0x0C in FEECON; wait for  
the read to be successful by monitoring FEESTA.  
5. Reset the part.  
Name  
Address  
Default Value  
Access  
FEEMOD  
0xFFFFF804  
0x0000  
R/W  
FEEMOD sets the operating mode of the flash control interface.  
Table 34 shows FEEMOD MMR bit designations.  
To remove or modify the protection, the same sequence is used  
with a modified value of FEEPRO. If the key chosen is the value  
0xDEAD, the memory protection cannot be removed. Only a mass  
erase unprotects the part, but it also erases all user code.  
Table 34. FEEMOD MMR Bit Designations  
Bit  
15:9  
8
Description  
Reserved.  
Reserved. This bit should always be set to 0.  
The sequence to write the key is illustrated in the following  
example (this protects writing Page 4 to Page 7 of the Flash):  
7:5  
Reserved. These bits should always be set to 0 except  
when writing keys. See the Sequence to Write the Key  
section.  
FEEPRO=0xFFFFFFFD;  
FEEMOD=0x48;  
FEEADR=0x1234;  
FEEDAT=0x5678;  
FEECON= 0x0C;  
//Protect pages 4 to 7  
//Write key enable  
//16 bit key value  
//16 bit key value  
// Write key command  
4
Flash/EE interrupt enable. Set by user to enable the  
Flash/EE interrupt. The interrupt occurs when a  
command is complete. Cleared by user to disable  
the Flash/EE interrupt.  
3
Erase/write command protection. Set by user to  
enable the erase and write commands. Cleared to  
protect the Flash against the erase/write command.  
The same sequence should be followed to protect the part  
permanently with FEEADR = 0xDEAD and FEEDAT = 0xDEAD.  
2:0  
Reserved. These bits should always be set to 0.  
Rev. F | Page 52 of 104