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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
Data Sheet  
More information relative to the programmer’s model and the  
ARM7TDMI core architecture can be found in the following  
materials from ARM:  
At the end of this time, the ARM7TDMI executes the instruc-  
tion at 0x1C (FIQ interrupt vector address). The maximum  
total time is 50 processor cycles, which is just under 1.2 µs in a  
system using a continuous 41.78 MHz processor clock.  
DDI0029G, ARM7TDMI Technical Reference Manual  
DDI-0100, ARM Architecture Reference Manual  
The maximum interrupt request (IRQ) latency calculation is  
similar but must allow for the fact that FIQ has higher priority  
and may delay entry into the IRQ handling routine for an  
arbitrary length of time. This time can be reduced to 42 cycles if  
the LDM command is not used. Some compilers have an option  
to compile without using this command. Another option is to run  
the part in thumb mode where the time is reduced to 22 cycles.  
INTERRUPT LATENCY  
The worst-case latency for a fast interrupt request (FIQ)  
consists of the following:  
The longest time the request can take to pass through the  
synchronizer  
The minimum latency for FIQ or IRQ interrupts is a total of  
five cycles, which consist of the shortest time the request can  
take through the synchronizer plus the time to enter the  
exception mode.  
The time for the longest instruction to complete (the  
longest instruction is an LDM) that loads all the registers  
including the PC  
The time for the data abort entry  
The time for FIQ entry  
Note that the ARM7TDMI always runs in ARM (32-bit) mode  
when in privileged modes, for example, when executing  
interrupt service routines.  
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