Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
OVERVIEW OF THE ARM7TDMI CORE
The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be eight bits, 16 bits, or 32 bits. The
length of the instruction word is 32 bits.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are
•
Normal interrupt or IRQ, which is provided to service
general-purpose interrupt handling of internal and
external events.
The ARM7TDMI is an ARM7 core with four additional features.
•
•
•
•
T support for the thumb (16-bit) instruction set.
D support for debug.
M support for long multiplications.
I includes the EmbeddedICE module to support embedded
system debugging.
•
Fast interrupt or FIQ, which is provided to service data
transfers or communication channels with low latency.
FIQ has priority over IRQ.
•
•
•
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI), which can be used
to make a call to an operating system.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that is compressed into 16 bits,
called the thumb instruction set. Faster execution from 16-bit
memory and greater code density can usually be achieved by
using the thumb instruction set instead of the ARM instruction
set, which makes the ARM7TDMI core particularly suitable for
embedded applications.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
However, the thumb mode has two limitations.
•
•
Thumb code typically requires more instructions for the
same job. As a result, ARM code is usually best for
maximizing the performance of time-critical code.
The thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the
current program status register (CPSR) are usable. The
remaining registers are used for system-level programming and
exception handling only.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All excep-
tion modes have replacement banked registers for the stack
pointer (R13) and the link register (R14), as represented in
Figure 44. The fast interrupt mode has more registers (R8 to R12)
for fast interrupt processing. This means that interrupt processing
can begin without the need to save or restore these registers
and, thus, save critical time in the interrupt handling process.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with a 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
R0
USABLE IN USER MODE
R1
SYSTEM MODES ONLY
R2
R3
R4
EmbeddedICE (I)
R5
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch-
point registers that allow code to be halted for debugging purposes.
These registers are controlled through the JTAG test port.
R6
R7
R8_FIQ
R9_FIQ
R8
R9
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R10
R11
R12
R13
R14
R15 (PC)
R13_UND
R13_IRQ
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers can be inspected as well as the Flash/EE,
SRAM, and memory mapped registers.
R13_ABT
R14_ABT
R14_UND
R14_IRQ
R13_SVC
R14_SVC
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
CPSR
SPSR_FIQ
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
USER MODE
Figure 44. Register Organization
Rev. F | Page 39 of 104
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